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ADS-B 978 MHz (UAT) Receiver
- ADS-B (UAT) receiver offers a comprehensive solution for the reception of flight, traffic and weather information.
- Compatible with all FPGA, SoC and ASIC devices, the circuit has been design proven and field tested, clocking over 500 flight hours.
- Complies with the RTCA DO-282B.
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Parallel FLASH Memory Controller
- JEDEC® compliant FLASH memory controller ideal for interfacing to a wide range of parallel FLASH memory components such as the popular SST39 series from Microchip®.
- Features a fully synchronous command interface and a set of configurable timing parameters for compatibility with different devices.
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ADS-B 1090 MHz (ES) Receiver
- ADS-B (ES) receiver offers a comprehensive solution for the reception of flight and traffic information.
- Compatible with all FPGA, SoC and ASIC devices, the circuit has been design proven and field tested, clocking over 500 flight hours.
- Complies with RTCA DO-260B.
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Floating-point to Fixed-point Converter
- Converts 32-bit floating-point numbers to fixed-point representation. The fixed-point output has a configurable word and fraction width.
- Floating-point inputs are based on the IEEE 754 standard. The design features a high-speed, fully pipelined architecture with a 2 clock-cycle latency.
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UART Serial Interface Controller
- The UART_CONT IP Core is a robust UART-compliant serial interface controller capable of receiving and transmitting bits serially.
- It has a configurable data payload from 5 to 8-bits (with or without parity) and supports either 1 or 2 stop bits.
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SPI Master Serial Interface Controller
- The SPI_MASTER IP Core is an SPI compliant serial interface controller capable of driving up to 16 different slave devices in full-duplex operation.
- The controller receives data and instructions via the master instruction interface.
- These instructions are then processed by the controller core in order to generate the appropriate signals on the SPI bus.
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Floating-point Adder
- High-speed fully pipelined 32-bit floating-point adder/subtractor based on the IEEE 754 standard.
- Results have a latency of 4 clock cycles. Ideal for floating-point pipelines, arithmetic units and processors.
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Floating-point Multiplier
- High-speed fully pipelined 32-bit floating-point multiplier based on the IEEE 754 standard.
- Results have a latency of only 4 clock cycles. Ideal for floating-point pipelines, arithmetic units and processors.
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Binary-PSK Demodulator
- The BPSK_DEMOD IP Core is a 16-bit resolution Binary-PSK demodulator based on a multiply-filter-divide architecture.
- The design is robust and flexible and allows easy connectivity to an external ADC.
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Binary-FSK Demodulator
- BFSK_DEMOD is a precision Binary-FSK Demodulator IP Core based on a non-coherent receiver design.
- The demodulator is fully programmable, allowing for a varied range of symbol rates and mark/space tone frequencies.
- Input data samples may be either complex or real for support of either passband or baseband signals.
- The module allows easy connectivity to an external ADC with up to 16-bit signed input samples.
