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Compare 160 Other from 54 vendors (1 - 10)
  • SLM High-Speed Access & Test IP
    • The SLM High-Speed Access and Test (HSAT) IP combined with the TestMAX® ALE software uses standard high speed IO interfaces such as PCIe and USB, to get test, debug and monitoring data in and out of an SoC at Gigabit data rates and avoids the need for large numbers of test and interface pins.
    • Test time can be reduced because the link between the test time and GPIO data rate is eliminated. Further, this solution provides a key component for Synopsys Silicon Lifecycle Management solution allowing manufacturing tests to be repeated in-system and in-field as well as providing high speed access to PVT and functional monitor dat
    Block Diagram -- SLM High-Speed Access & Test IP
  • Key Value Store/Exact Match Search Engine
    • Parameterizable field and table sizes
    • Support for larger on-chip tables
    • Sharing data between logic and software
    Block Diagram -- Key Value Store/Exact Match Search Engine
  • Decision tree inference core
    • So_ip_idt core can be used create a decision tree directly in hardware. It can create DTs with univarite, multivariate and non-linear tests.
    • Creating DTs directly in hardware results in the significant increase of DT inference speed, compared with the traditional software-based approach.
    Block Diagram -- Decision tree inference core
  • FPGA Scrubber Controller
    • GRSCRUB is an FPGA supervisor responsible for programming and scrubbing the FPGA configuration memory to prevent the accumulation of radiation-induced errors.
    • The GRSCRUB IP currently supports the AMD/Xilinx Kintex UltraScale and Virtex-5 FPGA families.
    Block Diagram -- FPGA Scrubber Controller
  • 3D LUT Intel® FPGA IP
    • As a part of the Video and Vision Processing (VVP) Suite Intel® FPGA IP, the 3D look-up table (LUT) Intel® FPGA IP provides an efficient solution for video color space and dynamic range conversions, chroma keying, and the creation of artistic effects.
    Block Diagram -- 3D LUT Intel® FPGA IP
  • ARINC429 Verification IP
    • Available in Verilog, System Verilog, and UVM.
    • Support for Bipolar RZ encoding
    • Integration friendly
    • Supports a wide variety of error injection scenarios.
    Block Diagram -- ARINC429 Verification IP
  • ARINC 708A Verification IP
    • Available in Verilog, System Verilog, and UVM.
    • Control Word information can be user-configurable / Random. (Protected By parity).
    • Data word header will be according to the 270 271 label Frame received from Control Word.
    • Support for Hazards, Faults, and Errors.
    Block Diagram -- ARINC 708A Verification IP
  • I3C
    • Innosilicon’s I3C (Improved Inter Integrated Circuit) is enhanced with I2C protocol and is compatible with I2C
    • It adds new functions, including higher transmission speed, in-band interrupt, CRC check, and so on
    • Now, the I3C protocol is divided into MIPI and JEDEC
    • Usually, MIPI I3C is applied in sensor/IoT data transmission, and JEDEC I3C is applied in storage chip configuration
    Block Diagram -- I3C
  • Ultra-low-power 60 GHz radar-on-chip
    • CSEM has developed a low-cost, ultra-low-power 60 GHz MIMO FMCW PHY that can be integrated into radar-on-chips with custom digital processing for specific applications.
    • This solution leverages CSEM’s decades of experience in ultra-low-power RF CMOS system-on-chip design.
    Block Diagram -- Ultra-low-power 60 GHz radar-on-chip
  • cjTAG IEEE 1149.7 Compact TAP Controller
    • Supports IEEE 1149.7 classes 0–5 (selected through hardware configuration parameter)
    • Partitioned along IEEE 1149.7-specified functional boundaries (so that only the required hardware is included):
    • Supports all mandatory and optional scan formats: JScan0–3, SScan0–3, OScan0–7, and MScan
    • Supports all mandatory and optional cJTAG commands
    Block Diagram -- cjTAG IEEE 1149.7 Compact TAP Controller
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