Other

Analyzes on-chip signals and interfaces.
Measure the performance and verify the functionality
“Logic-analyzer” type visibility of internal signals not normally detectible off-chip
Run-time configurable

Single database: Import and capture memory map information into a single database (IP-XACT)
Graphical edition: IP memory map capture & management GUI, system memory map capture & management GUI, system level schematic configurability, GUI with linting cross-checking editor
Parameterization: including configurable and conditional properties, custom-specific access types, and register modes
SystemRDL compiler: full support of version 1.0, limited support for version 2.0

Project management: Design navigation and data aggregation
HDL import: Automatic import of structural RTL into a valid IP-XACT design with the support of SystemVerilog, Verilog, and VHDL languages
IP Packaging: Aggregate component information from different sources in a structured and standard-based format for several design tasks and teams (automatic mapping of bus interfaces, specification of the views with complete fileSet for various skills)
SoC assembly: Powerful rule-based connectivity, bus interface detection, bus/signal split/tie/open, hierarchical connection, glue logic insertion, feedthrough

Comprehensive traceability: Create and maintain traceability between requirements, specifications, hardware designs, software code, tests, and documentation.
System-of-systems integration: Harmonize disparate systems for end-to-end traceability of all artifacts.
Tool integration: Link information from leading tools in requirements management, code repository, EDA, software engineering, verification, test, and documentation.
Multi-domain linking: Enable traceability across multiple domains, providing a comprehensive understanding of the design.