Network-on-Chip (NoC) IP

Welcome to the ultimate Network-on-Chip (NoC) IP hub! Explore our vast directory of Network-on-Chip (NoC) IP.

A network on chip (NoC) is an in-chip network, often in a SoC, that connects IP blocks and components and routes data packets among them using switches. Often the NoC provides cache coherency among different components accessing memory.

All offers in Network-on-Chip (NoC) IP

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Compare 19 Network-on-Chip (NoC) IP from 10 vendors (1 - 10)

Tessent NoC Monitor
- Full transaction and trace-level visibility of traffic
- Wide range of measurements, analytics statistics: transactions, bus cycles, latency, duration, beats, concurrency
Tessent Bus Monitor
- Full transaction and trace-level visibility of on-chip bus traffic
- Wide range of measurements, analytics statistics: Transactions, Bus cycles, latency, duration, beats, bus concurrency
- Supports AXI, ACE, ACE-lite
- Run-time configurable
Ncore 3 Coherent Network-on-Chip (NoC)
- Supports multiple coherent agents, including Armv9 and RISC-V CPU clusters
- AMBA CHI-E, CHI-B and ACE interoperability, as well as ACE-Lite and AXI
- Low-latency proxy caches for efficient and quick integration of hardware accelerators into the coherent domain
- Configurable last-level caches
FlexNoC 5 Interconnect IP
- Physical Awareness for faster timing closure
- Higher margins
- Fewer wires
FlexNoC 5 Option For Scalability and Performance Critical Systems
- Scales from 10s to 100s of IP blocks
- Automatically generates ring, mesh and torus networks
- View and edit generated topologies
FlexNoC Functional Safety (FuSa) Option helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults.
- ARM® Cortex®-R5 and Cortex-R7 processor port checking
- Hardware duplication and redundancy
- Custom ECC and parity generation and checking
Coherent Network-on-chip (NoC) IP
- Layered, scalable, configurable, and physically aware configurable NoC
Non-coherent Network-on-chip (NoC) IP
- Layered, scalable, physically aware configurable NoC
NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
- Easy to integrate the NoC Silicon IP using interface
- N master and M slave ports based on customer requirement
- Supports wide range of memory map.
High speed NoC (Network On-Chip) Interconnect IP
- High Performance
- Low Power Consumption
- Smaller Area