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Peripheral Controller IP

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Search (37)
Compare 37 Peripheral Controller IP from 14 vendors (1 - 10)
  • Quad SPI Controller
    • Configurable SPI modes
    • Supports programmable SPI clocking modes
    • Programmable interrupt on SPI-done
    Block Diagram -- Quad SPI Controller
  • FPGA Supervisor
    • FPGA configuration
    • Mapping FPGA frame addresses
    • Blind scrubbing
    Block Diagram -- FPGA Supervisor
  • I2C Controller
    •  Dual mode IP (master and slave mode).
    •  Supports different modes of transfer .
    •  Supports DMA interface also .
    • Separate clock domain for IP Core functionality and Host Interface.
    Block Diagram -- I2C Controller
  • I3C Master and Slave Dual Role Controller
    • Compliant with the latest version of the MIPI I3C specification
    • Legacy I2C
    • I3C features
    • Low Power
    Block Diagram -- I3C Master and Slave Dual Role Controller
  • AHB Cache Controller
    • The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave processor interface and a 32-bit master interface to the memory subsystem. The processor and memory interfaces are natively AHB5 and can easily be reduced to AHB-lite. 
    • The cache controller core supports a four-way associative cache memory and implements a Least Recently Used (LRU) replacement policy.
    Block Diagram -- AHB Cache Controller
  • ATAPI Host Controller
    • Supports interface between processor and hard disk.
    • Supports parallel ATA/ATAPI-6 mode of operation.
    • Supports ATA PIO mode 0,1,2,3, and 4.
    • Supports ATA Multi Word DMA mode 0, 1 and 2.
    Block Diagram -- ATAPI Host Controller
  • 8530 Multi-Protocol Controller
    • Hardware features
    • Communication protocol features
    • Encode/decode of NRZ (Non-Return to Zero)
    Block Diagram -- 8530 Multi-Protocol Controller
  • 8251 Serial Controller
    • RS-232-C protocol support
    • Baud rate generator or timer output selectable as Tx/Rx clock
    • Asynchronous communication only
    • Serial interrupt support
    Block Diagram -- 8251 Serial Controller
  • 8254 Programmable Timer
    • Three independently operated 19-bit counters
    • Binary/BCD count operation
    • Multiple Latch command for easy monitoring
    • Counter Latch command
    Block Diagram -- 8254 Programmable Timer
  • PS/2 Keyboard controller, fully configurable
    • PS/2 core is used to communicate with either keyboard or mouse device
    • PS/2 core can be configured to use single or dual connection signals within the same core
    • AHB or WISHBONE SoC Interconnection Rev B compliant interface
    • PS/2 can operate in pooling or interrupt mode
    Block Diagram -- PS/2 Keyboard controller, fully configurable
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Semiconductor IP