IP Catalog > Interface IP Cores > Ethernet IP

Ethernet IP

Ethernet IP cores, including 112G and 224G PHYs, up to 1.6T controllers, MACsec security modules, and Verification IP, offer optimized power, performance, area, and latency for automotive, HPC, AI, and IoT SoCs.

Ethernet is defined in a number of IEEE 802.3 standards. These standards define the physical and data-link layer specifications for Ethernet.

Explore our vast directory of Ethernet IP cores below

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Search (378)
Compare 378 Ethernet IP from 67 vendors (1 - 10)
  • Lithe Layer 2 Gigabit Ethernet Switching IP
    • The Lithe Layer 2 Gigabit Ethernet Switching IP is a comprehensive solution for building scalable and efficient network infrastructures.
    • Designed to operate at the data link layer of the OSI model, our Lithe Layer 2 IP offers advanced networking capabilities for local area networks (LANs), metropolitan area networks (MANs), and wide area networks (WANs).
    • With support for various networking protocols and features, our Lithe IP enables seamless connectivity, reliable data transmission, and efficient network management.
    Block Diagram -- Lithe Layer 2 Gigabit Ethernet Switching IP
  • ARINC664 Switch IP Core
    • ARINC664 Switch IP implements ARINC664 part 7 and provides switching functionality within the ARINC664 network.
    • As an implementation of ARINC664 Switch, IP switches/routes messages of different sizes and different time constraints to their destination with a predictable delay.
    Block Diagram -- ARINC664 Switch IP Core
  • ARINC664 End System IP Core
    • ARINC664 End System IP is an IP Core that implements ARINC664 part 7 and provides interface between aircraft LRUs and ARINC664 network.
    • As an implementation of End System, IP sends the user's messages of different sizes and different time constraints to their destination with a predictable delay.
    Block Diagram -- ARINC664 End System IP Core
  • Block Diagram -- 10-Gbps Ultra-Low Latency Ethernet MAC and PCS
  • 10/100/1000 Ethernet MAC DO-254 IP Core
    • The 10/100/1000 Ethernet MAC Controller DO-254 IP Core implements the Media Access Control as specified in the IEEE 802.3-2008 specification.
    • The Ethernet MAC Controller has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit. 
    Block Diagram -- 10/100/1000 Ethernet MAC DO-254 IP Core
  • TCP/UDP Offload Engine
    • Full hardware TCP/UDP protocol stack realize both high performance and guaranteed delivery
    • The TCP/UDP offload engine supports simultaneous connection of more than 10,000 sessions on a single core, which is a feature of our IP along with its high quality and performance.
    Block Diagram -- TCP/UDP Offload Engine
  • Ethernet 200G Synthesizable Transactor
    • Supports 200G as per 802.3bs:
    • Supports 200GBase_KR8
    • Supports 200GBase_KR4
    • Supports 200GBase_KR2
    Block Diagram -- Ethernet 200G Synthesizable Transactor
  • Ethernet 25GBase-R/KR Synthesizable Transactor
    • Supports 25GBase-R/KR interfaces as per the specifications defined in IEEE 802.3 802.3ba
    • Supports 25G :
    • Supports 25GBase_R
    • Supports 25GBase_KR
    Block Diagram -- Ethernet 25GBase-R/KR Synthesizable Transactor
  • Ethernet 400G Synthesizable Transactor
    • Supports 400G as per 802.3bs:
    • Supports 400GBase_KR4
    • Supports 400GBase_KR8
    • Supports 400GBase_KR16
    Block Diagram -- Ethernet 400G Synthesizable Transactor
  • Ethernet 40G Synthesizable Transactor
    • Supports 40G as per 802.3ba:
    • Supports XLGMII
    • Supports 40GBase-KR4/40GBase-CR4/40GBase-SR4/40GBase-LR4
    • Supports 40GBase-R
    Block Diagram -- Ethernet 40G Synthesizable Transactor
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