IP Catalog > Interface IP Cores > Ethernet IP

Ethernet IP

Ethernet IP cores, including 112G and 224G PHYs, up to 1.6T controllers, MACsec security modules, and Verification IP, offer optimized power, performance, area, and latency for automotive, HPC, AI, and IoT SoCs.

Ethernet is defined in a number of IEEE 802.3 standards. These standards define the physical and data-link layer specifications for Ethernet.

Explore our vast directory of Ethernet IP cores below

All offers in Ethernet IP
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Search (386)
Compare 386 Ethernet IP from 67 vendors (1 - 10)
  • 10-Gbps Ultra-Low Latency Ethernet MAC and PCS
    • The core is designed using advanced design techniques leading to unmatched ultra-low gate count utilization and amazing latency performances.
    • The 10G IP core support both 16b (644MHz) and 32b (322MHz) modes, and can support full wire line speed with a 64-byte packet length. It also supports back-to-back or mixed length traffic with no dropped packets.
    Block Diagram -- 10-Gbps Ultra-Low Latency Ethernet MAC and PCS
  • 10/100 Mbit Ethernet MAC
    • The GRETH core implements a 10/100 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface.
    • The core implements the 802.3-2002 Ethernet standard. Receive and transmit data is autonomously transferred between the Ethernet MAC and the AMBA AHB bus using DMA transfers.
    Block Diagram -- 10/100 Mbit Ethernet MAC
  • 10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface
    • Full implementation of IEEE 802.3-2002
    • 10/100/1000 MBit operation
    • AMBA AHB host interface with DMA
    • Low CPU overhead
    Block Diagram -- 10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface
  • GEMAC OVC
    • Gigabit Ethernet Media Access Control (MAC) SystemVerilog OVC VIP is fully documented,off-the-shelf component for the Developers of the Gigabit Ethernet MAC.
    • Full Programmability and versatility of the OVC enables connection to any standard IEEE 802.3 based GEMAC device and supports application of Stimulus to the generic microcontroller Interface as well as PHY Interface
    Block Diagram -- GEMAC OVC
  • Gigabit Ethernet Media Access
    • The GEMAC (Gigabit Ethernet Media Access Controller) core implements the Ethernet Media Access Control (MAC) protocol according to IEEE 802.3 specification.
    • The MAC has a standard Gigabit Media Independent Interface (GMII) to connect to any PHY interface.
    • The core can be used in various integrated applications. A single channel MAC with PCI controller would provide an ideal solution for inexpensive NIC cards.
    Block Diagram -- Gigabit Ethernet Media Access
  • 7990 Local Area Network Controller
    • The SI79C90 Local Area Network Controller for Ethernet is an IP core designed to greatly simplify interfacing a microcomputer or minicomputer to an IEEE 802.3 / Ethernet Local Area Network.
    • The SI 79C90 interfaces a minicomputer or microcomputer with the IEEE 802.3 / Ethernet Local Area Network. Its versatile bus interface logic interfaces the peripheral chip with Intel, Motorola, Zilog or AMD microprocessors.
    Block Diagram -- 7990 Local Area Network Controller
  • Gigabit Ethernet Transceiver
    • SMS4000 is a fully integrated CMOS transceiver compliant with IEEE 802.3z standard. It contains all necessary Clock synthesis, Clock Recovery, Serializer, Deserializer, High-speed, Low jitter PECL serial input-output interface, Comma detect for 8B/10B encoded data frame alignment functionality’s.
    • Digital controller interface is realized with 10-bit parallel operation which allows use of 125/106.25 Mhz reference Clock. The transceiver includes extensive Analog and digital Signal Detect capability which indicates valid signal presence at its receive inputs, through verification of valid 8B/10B characters, and valid control ( K ) character occurrence at permitted intervals.
    Block Diagram -- Gigabit Ethernet Transceiver
  • Block Diagram -- DSP 10/100 100B-TX Ethernet PHY
  • Intel® Stratix® 10 FPGA H-Tile Hard IP for Ethernet Intel® FPGA IP Core
    • Intel® Stratix® 10 FPGA H-Tile FPGA production devices include a configurable, hardened protocol stack for Ethernet that is compatible with the IEEE 802.3 High Speed Ethernet Standard.
    Block Diagram -- Intel® Stratix® 10 FPGA H-Tile Hard IP for Ethernet Intel® FPGA IP Core
  • Triple-Speed Ethernet FPGA IP
    • The Triple-Speed Ethernet FPGA IP core consists of a 10/100/1000 Mbps Ethernet media access control (MAC) and physical coding sublayer (PCS) Intellectual Property (IP).
    • This IP function enables FPGAs to interface to an external Ethernet PHY device, which interfaces to the Ethernet network.
    Block Diagram -- Triple-Speed Ethernet FPGA IP
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