Analog Front Ends IP

Embedded Computation Engine for utility billing applications
Low noise Programmable Gain Amplifier (PGA), to reach the best class accuracy with each type of sensors
Embedded power management for the best resilience to power supply noise

The ODT-AFE-4T4R-12nm is an ultra-high-performance AFE designed in a 12nm CMOS process.
The AFE includes 2 IQ Pairs of Tx and Rx for the FR2 band, and combines them with 2 additional IQ Pairs of Tx and Rx for the FR1 band clocked at a lower sample rate.

The ODT-AFE-1T1R-12 is an ultra-high-performance AFE designed in a 12nm process.
The AFE includes 1 IQ Pairs of Tx and Rx for either the FR1 or FR2 band. This is comprised of two 12-bit 2GSPS ADCs, and two 12-bit 2GSPS DACs.
This AFE also includes multiple capless LDOs, a voltage/current reference, and a low jitter 2 GHz PLL

The ODT-AFE-2T2R-GF22FDX is an ultra-highperformance AFE designed in a Global Foundries 22nm process.
The AFE includes two 12-bit, 4GSPS I/Q ADC pairs, two 14-bit, 8GSPS I/Q DAC pairs, four capless LDOs, one Bandgap reference and one temperature sensor and includes an integrated 3rd party PLL.

The ODT-AFE-6B1G-28HPCPT is a highperformance I/Q ADC and I/Q DAC designed in a 28nm CMOS process.
The 6-bit, 1.056GSPS I/Q ADC supports input signals up to 400 MHz and features a differential full-scale range of 0.6Vpp and excellent static and dynamic performance.
The ADC architecture is optimized to maximize performance while minimizing power and area consumption.

NEXUS28Z is a CMOS integrated circuit, implementing highly integrated, mmWave, agile beamforming offering high performance and configurability for target applications.
NEXUS28Z delivers a versatile combination of high performance and low power consumption, operating in the frequency range of 24-31GHz. It consists of 8 TX/RX front-ends, which can be split in 2 orthogonal polarizations (4 horizontal and 4 vertical).

The Analog-Frontend (AFE) IP consists of programmable current and voltage preamplifier followed by a Successive Approximation Register (SAR) architecture ADC using charge-redistribution technique.
The ADC IP is configurable regarding resolution (6-13 bit) and sample rate (up to 10kS/s). The preamplifier offers programmable gain from 0.5 to 4. The input voltage range is quasi-rail-to-rail guaranteeing more than +- 1.7 V @ 1.8 V power supply. An optional calibration technique can be applied to compensate degraded mismatch behavior of technology capacitors.
The overall power consumption of the AFE IP sums up with 10.5 uW at 1 kHz input signal.

The WEA7186F55 is a front end for wireless microwave transceivers operating in the E-Band
Implemented in a ST Micro Silicon Germanium B55 process
The WEA7186F55 integrates a LNA path, a Power Amplifier together with Bias and Gain Control blocks.

The MVCTCH01 ASIC is an ultra-low power and high-sensitivity 8-channel capacitive touch interface that is designed to be easily integrated with capacitive touch pads.
Ultra-low power operation is achieved by using a novel capacitive-to-digital converter, making it suitable for battery powered and portable devices.

The MVUS01 ultrasound transducer interface is the first generation of high-voltage (HV) ultrasound ASICs intended for portable medical imaging probes and other markets.
The chip supports pulsing ultrasonic transducers, with excitation voltages of up to 50V, and has high gain and low noise receivers, for increased sensitivity to ultrasonic echoes.