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Compare 1,155 IP for SMIC from 39 vendors (1 - 10)
  • eFPGA Soft IP
    • These eFPGA IP cores offer designers the flexibility to tailor resources to their application requirements, available as either Soft RTL or Hard GDSII IP.
    • Our standard-cell-based approach facilitates rapid porting to new process geometries or variants, including industrial and rad-hard grade versions.
    Block Diagram -- eFPGA Soft IP
  • Complete USB Type-C Power Delivery IP
    • Mixed signal Analog Front End Macros for 65n, 130n, 150nm, and 180n technologies.
    • RTL code from AFE to I2C compatible register set.
    • Stand alone C code for Protocol, Device Policy Manager, and System Policy Manager.
    • IP demonstration & development board, with compliance reports. 
    • Full chip integration of USB Type-C, and associated software.
    Block Diagram -- Complete USB Type-C Power Delivery IP
  • High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
    • Fractional-N digital PLL architecture, using an LC-tank oscillator
    Block Diagram -- High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
  • Low Voltage, Low Power Fractional-N PLLs
    • Low power, suitable for IoT applications
    • Good jitter, suitable for clocking digital logic.
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
    Block Diagram -- Low Voltage, Low Power Fractional-N PLLs
  • General Purpose Fractional-N PLLs
    • Low power, suitable for logic clocking applications
    • Extremely small die area, using a ring oscillator
    • Twelve bits fractional resolution
    Block Diagram -- General Purpose Fractional-N PLLs
  • Fractional-N PLLs for Performance Computing
    • Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 4GHz
    • Reference clock from 10MHz to 500MHz
    Block Diagram -- Fractional-N PLLs for Performance Computing
  • 24-bit Cap-less ADC 106 dB SNR
    • I2C and APB control interface
    • Embedded low noise voltage regulator for best resilience to power supply noise
    • Low BoM and capacitor-less input connection
    • High dynamic range for high quality recording in far-field applications
    Block Diagram -- 24-bit Cap-less ADC 106 dB SNR
  • 24-bit Cap-less ADC 106 dB SNR low power and low latency 3 channels
    • I2C and APB control interface
    • Embedded low noise voltage regulator for best resilience to power supply noise
    • Low BoM and capacitor-less input connection
    • High dynamic range for high quality recording in far-field applications
    Block Diagram -- 24-bit Cap-less ADC 106 dB SNR low power and low latency 3 channels
  • Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
    • Low noise: high power Supply Rejection Ratio (PSRR): - 65 dB at F < 10 kHz
    • Low intrinsic noise: 20 uVRMS at 10 Hz to 20 kHz
    • Low Bill-of-Material: optimized in density for the best trade-off for the given output current and input voltage range
    • Cost efficient solution compared to external Power Management.
    Block Diagram -- Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
  • I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus

    • The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I2C Bus in Standard-Mode (100 Kbit/s) / Fast-Mode (400 Kbit/s) / Fast-Mode Plus (1 Mbit/s) / Hs-Mode (3.4+ Mb/s) / Ultra Fast-Mode (5 mbit/s).

      The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.

      The DB-I2C-MS-APB is a Master/Slave I2C Controller that in Master Mode controls the Transmit or Receive of data to or from slave I2C devices while in Slave Mode allows an external I2C Master device to control the Transmit or Receive of data.

    Block Diagram -- I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus
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