AMBA AHB / APB/ AXI IP

The AHB Verification IP provides a complete solution for Verification of AMBA 3.0 AHB-Lite protocol v1.0 component of a SOC or ASIC
The AHB-Lite Verification IP is fully compliant with standard AMBA 3 AHB-Lite Specification
AMBA 3.0 AHB-Lite VIP is supported natively in SystemVerilog and UVM

The AMBA-AXI VIP provides a complete solution for verification of AMBA-AXI protocol version 2.0
The AXI verification IP is fully compatible with standard AXI 3 protocol
This VIP is supported natively in System Verilog UVM

The AXI MATRIX-IP component is a multi-layer interconnect implementation of the AXI protocol, which is designed for high-performance, high-frequency system designs.
AXI MATRIX-IP is highly configurable with the capacity to handle up to 16 Masters and Slaves. IP can be configured to support AXI3, AXI4-Lite or AXI4

The RapidlO-AXI Bridge (RIO-AXI Bridge) is a highly flexible and configurable IP used along with the native RapidlO Controller (GRIO) to provide RapidlO interface on one side and AXI interface on the system side.
The Bridge has been architectured to interface with a RapidlO controller used as a Host or device.
The RIO-AXI BRIDGE uses high speed multi-channel DMA Messaging and data streaming controllers to match the bandwidth requirements of the RIO solution.

The AHB 4 Channel DMA Controller is a multiple-channel direct memory access controller.
The DMA IP Core is a Verilog HDL design that can be used in ASIC, Structured ASIC and FPGA designs.
The design is intended to be used with AMBA based systems as a controller to transfer data directly from system memory to memory or system memory to peripheral device or IP Core.

The AHB Arbiter arbitrates for the AHB bus among as many as four AHB master components.
The AHB Arbiter implements a round-robin arbitration algorithm to AHB Master components that are requesting use of the bus.
Only one master component may control a given phase of the AHB transaction at a given time.

The AHB Channel provides the necessary infrastructure to connect as many as 7 AHB Slaves (numbered 1-7) to an AHB bus Master.
The AHB Channel performs a combinational decode on the incoming AHB address to produce the block selects for the various AHB Slaves.
The address decoder contained in the AHB Channel has one area of memory reserved for a configurable remap application.

The AHB External Bus Interface (EBI) allows a CPU or AHB Master component (such as a DMA core) to transmit and receive data to an external device such as an external SRAM or Parallel Flash device.
The number of read wait states, the number of write wait states, and the memory width are all configurable through the APB register interface of the EBI. The EBI allows word, half-word, and byte width addressing to 32-bit, 16-bit, and 8-bit external devices.

The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction.
It is expected that the AXI clock and the AHB clock are derived from the same clock source, and that the period of the AHB Lite clock is an integer multiple of the AXI clock in the range [1,16].

The AHB Low Power Subsystem is an AMBA® based system that is useful as the basic digital infrastructure for building low power SOCs.
The subsystem contains a flexible Power Management Unit that controls the power sequence of the CPU as well as the APB peripherals.
The PMU can easily be extended to control additional cores, peripherals and even mixed signal subsystems on the same SOC.