AMBA AHB / APB/ AXI IP

StarNoC-500 is the vendor's first self-developed interconnect fabric IP with cache coherence support, supporting the construction of multi-cores and SoC.

The GRETH core implements a 10/100 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface.
The core implements the 802.3-2002 Ethernet standard. Receive and transmit data is autonomously transferred between the Ethernet MAC and the AMBA AHB bus using DMA transfers.

GRCAN is a CAN 2.0 IP core that implements an internal CAN controller and an AHB DMA backend.
The APB bus is used for configuration, control and status handling and the AHB bus is used for retrieving and storing CAN messages via the DMA engine.

Supports AHB bus interface to the ARM CPU.
User interface designed for high speed access to any slave devices on the AHB Bus.
User specified single or burst data access on the AHB interface and user interface.
Handles wait state insertion by any slave devices.

Supports AHB bus interface to the ARM CPU.
User interface designed for high speed access to two sets of on-chip or off-chip modules.
Four write buffers to process posted write.
Dual read buffers to process CPU read.

The ORBIT On-Chip Interconnect (OIC) delivers exceptional performance, and SoC design flexibility based on automated end-to-end interconnect generation flow.
It enables high-speed routing with pre-calculated routing path details and supports higher speed, low latency, and floorplan flexibility.

The RapidlO-AXI Bridge (RIO-AXI Bridge) is a highly flexible and configurable IP used along with the native RapidlO Controller (GRIO) to provide RapidlO interface on one side and AXI interface on the system side.
The Bridge has been architectured to interface with a RapidlO controller used as a Host or device.
The RIO-AXI BRIDGE uses high speed multi-channel DMA Messaging and data streaming controllers to match the bandwidth requirements of the RIO solution.