Analog Subsystem IP
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8
Analog Subsystem IP
from 3 vendors
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8)
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Sleep Management Subsystem
- Power-On-Reset
- Programmable relaxation oscillator
- Low Power Comparator
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Power Management Subsystem
- The agilePMU Subsystem is an efficient and highly integrated Power Management Unit for SoCs/ASICs.
- Featuring a Power-On-Reset (POR), multiple Low Drop-Out (LDO) regulators, and an associated reference generator.
- The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities.
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Sensor Interface Subsystem
- The agileSensorIF Subsystem is an efficient and highly integrated sensor interface for SoCs/ASICs.
- Featuring multiple Analog-to-Digital Converters (agileADC), Digital-to-Analog Converters (agileDAC), low-power programmable analog comparators (agileCMP_LP), and an associated reference generator (agileREF).
- The agileSensorIF Subsystem enables easy interaction with the analog world.
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Integrated Droop Response System
- Observable
- Tightly Coupled
- Process Portable
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UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)
- 48-Gsps peak sample rate
- 8 bit resolution
- UCIe SP (16x lanes at 16Gbps) with streaming controller
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UCIe based 12-bit 12-Gsps Transceiver (ADC/DAC/PLL/UCIe)
- 12-Gsps peak sample rate
- 12 bit resolution (programmable)
- UCIe SP (16x lanes at 16Gbps) with streaming controller
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8-bit 48-Gsps Transceiver (ADC/DAC/DLL)
- 48-Gsps peak sample rate
- 8 bit resolution
- SMALLER than competing solutions
- LOWER POWER than competing solutions
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12-bit 12-Gsps Transceiver (ADC/DAC/PLL)
- 12-Gsps peak sample rate
- 12 bit resolution (10-bit option)
- SMALLER than competing solutions
- LOWER POWER than competing solutions