DMA Controller IP
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The Direct Memory Access (DMA) controllers enable the movement of blocks of data from peripheral to memory, memory to peripheral, or memory to memory without burdening the processor.
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DMA Controller IP
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27
DMA Controller IP
from 13 vendors
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10)
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General Purpose & Bridge DMA
- DMA-GP Core
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DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List
- 2 Dedicated DMA Channels, 1 each for data transfers for the following:
- Command and Status via AXI4-Stream Interfaces - 1 set per MM2S & S2MM:
- MM2S & S2MM DMA Controllers:
- Individual Interface Data Widths: 8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024.
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DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
- 2 Dedicated DMA Channel
- Command and Status via Scatter Gather List (SGL)
- Arbiter – Round Robin
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Peripheral Direct Memory Access Controller
- AMBA AXI4-Lite slave bus
- AMBA AXI4 master bus
- Configurable number of peripheral channels
- 8, 16, 32 bits data transfer modes
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Peripheral Direct Memory Access Controller
- AMBA APB3 slave bus
- AMBA AHB-Lite master bus
- Configurable number of peripheral channels
- 8, 16, 32 bits data transfer modes
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AXI4 to/from Stream DMA
- Independent stream-to-memory, and memory-to-stream paths
- Up to 16 commands per direction with 32-bit or 64-bit address offset and 16-bit transfer length
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Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
- 2 Dedicated DMA Channels
- AXI4 Interfaces
- Interrupt Controller
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AXI4 to/from AXI4-Stream Scatter-Gather DMA
- AXI4 Memory Mapped to Stream & Stream to Memory Mapped DMA
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Stream Buffer Controller
- Supports up to 16 write and read streams (depending on product options)
- Configurable status flags for write and read path
- Vendor-independent implementation
- Available with Avalon or AMBA-AXI interface
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AHB AES with DMA
- Advanced Encryption Standard FIPS 197 compliant
- Implements Rijndael algorithm
- Efficient “Tower Field” SBox implementation
- Encrypts / Decrypts 128 bit data blocks