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DMA Controller IP

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The Direct Memory Access (DMA) controllers enable the movement of blocks of data from peripheral to memory, memory to peripheral, or memory to memory without burdening the processor.

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Compare 10 DMA Controller IP from 6 vendors (1 - 10)
  • Multi-Channel Flex DMA IP Core for PCI Express
    • The Multi-Channel DMA IP Core for PCI-Express is a powerful PCIe Endpoint with multiple industry standard AXI Interfaces.
    • Up to 16 independent AXI Stream Slaves write DMA Data to the Host. Up to 16 AXI Stream Masters read DMA Data from the Host and present it to the User Logic.
    • Each channel operates on a separate memory area. Additional 8 AXI4 Masters are available to interface full AXI or AXI-Lite peripherals with the Host.
    Block Diagram -- Multi-Channel Flex DMA IP Core for PCI Express
  • AMBA AHB Direct Memory Acess (DMA) Controller
    • Multiple independent DMA channels with direct AHB bus interface.
    • DMA transfers between AHB memory devices and I/O ports.
    • Scatter-gather allows DMA to merge multiple data source to contiguous space.
    • Supports both hardware initiated transfer and software initiated transfer.
    Block Diagram -- AMBA AHB Direct Memory Acess (DMA) Controller
  • DMA Controller
    • Multiple independent DMA channels
    • Designed with synthesizable HDL for ASIC and PLD implementations in variou system environments
    • Each channel programmable to two types of DMA transfers: memory-to-memory and memory-to-I/O data transfer.
    • Supports both hardware initiated transfer and software initiated transfers.
    Block Diagram -- DMA Controller
  • SG DMA Controller, 1-16 DMA Channels, AHB5 Master Interface
    • The DB-DMAC-MC-AHB5 & DB-DMAC-MC-AHB-Lite Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 1 – 16 independent data transfers.
    • The Direct Memory Access (DMA) Controller IP Core contains 1 - 16 DMA Controller Engines (i.e. DMA Channels), with a unified AHB Master Read/Write interconnects.
    • The DB-DMAC-MC-AHB excels at high data throughput on both small and large data sets. Standard IP releases of number of DMA Controller Engines are 1, 2, 4, 8, and 16.
    Block Diagram -- SG DMA Controller, 1-16 DMA Channels, AHB5 Master Interface
  • SG DMA Controller, 1-16 DMA Channels, AXI4 / AXI3 Master Interfaces
    • The DB-DMAC-MC-AXI Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 1 – 16 independent data transfers.
    • The Direct Memory Access (DMA) Controller IP Core contains 1 - 16 DMA Controller Engines (i.e. DMA Channels), with user selectable AMBA AXI4 / AXI3 Master Read/Write interconnects.
    • The DB-DMAC-MC-AXI excels at high data throughput on both small and large data sets. Standard IP releases of number of DMA Controller Engines are 1, 2, 4, 8, 16.
    Block Diagram -- SG DMA Controller, 1-16 DMA Channels, AXI4 / AXI3 Master Interfaces
  • Scatter-Gather DMA Controller
    • Supports up to 16 physical channels
    • Up to 8 sub-channels per physical channel
    • Four priority levels using round-robin arbitration (weighted or simple)
    • WISHBONE bus widths from 8 to 128 bits
    Block Diagram -- Scatter-Gather DMA Controller
  • 8237 DMA Controller
    • 24-bit length address register
    • 16-bit length count register
    • 4 independent DMA channels
    • 4 clock / 1 bus cycle
    Block Diagram -- 8237 DMA Controller
  • AXI Central DMA Controller
    • AXI4 interface for data transfer
    • Independent AXI4-Lite slave interface for register access
    • Independent AXI4 Master interface for optional Scatter/Gather function
    • Optional Data Re-Alignment Engine
  • XPS Central DMA Controller
    • Connects as a 32-bit master/slave on PLB V4.6 buses of 32, 64 or 128 bits
    • Provides a single physical channel of Direct Memory Access between a source address and a destination address
    • Provides programmable registers for source address, destination address and transfer length
    • Supports different clock domains for Master and Slave interfaces
  • AXI DMA Controller
    • AXI4 compliant
    • Optional Scatter/Gather (SG) DMA support. When Scatter/gather mode is not selected the IP operates in Simple DMA mode.
    • Primary AXI4 Memory Map and AXI4-Stream data width support of 32, 64, 128, 256, 512, and 1024 bits
    • Optional Data Re-Alignment Engine
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