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DMA Controller IP

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The Direct Memory Access (DMA) controllers enable the movement of blocks of data from peripheral to memory, memory to peripheral, or memory to memory without burdening the processor.

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Search (29)
Compare 29 DMA Controller IP from 14 vendors (1 - 10)
  • Block Diagram -- General Purpose & Bridge DMA
  • SG DMA Controller, 1-16 DMA Channels, AXI4 / AXI3 Master Interfaces
    • The DB-DMAC-MC-AXI Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 1 – 16 independent data transfers.
    • The Direct Memory Access (DMA) Controller IP Core contains 1 - 16 DMA Controller Engines (i.e. DMA Channels), with user selectable AMBA AXI4 / AXI3 Master Read/Write interconnects.
    • The DB-DMAC-MC-AXI excels at high data throughput on both small and large data sets. Standard IP releases of number of DMA Controller Engines are 1, 2, 4, 8, 16.
    Block Diagram -- SG DMA Controller, 1-16 DMA Channels, AXI4 / AXI3 Master Interfaces
  • SG DMA Controller, 1-16 DMA Channels, AHB5 Master Interface
    • The DB-DMAC-MC-AHB5 & DB-DMAC-MC-AHB-Lite Verilog RTL IP Core is a Multi-Channel DMA Controller supporting 1 – 16 independent data transfers.
    • The Direct Memory Access (DMA) Controller IP Core contains 1 - 16 DMA Controller Engines (i.e. DMA Channels), with a unified AHB Master Read/Write interconnects.
    • The DB-DMAC-MC-AHB excels at high data throughput on both small and large data sets. Standard IP releases of number of DMA Controller Engines are 1, 2, 4, 8, and 16.
    Block Diagram -- SG DMA Controller, 1-16 DMA Channels, AHB5 Master Interface
  • AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Commands Streams
    • The DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.
    • Descriptor Control is managed by Commands that stream in via dedicated Command, AXI4-Stream Interface, with resulting output Status on Status Stream, AXI4-Stream Interfaces.
    Block Diagram -- AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Commands Streams
  • AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Descriptors
    • The DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.
    • Control is managed by Descriptors initialized by the Control/Status Register Interface, with the Descriptors read in from memory via the AXI4 MM Read Channel and processed with the DMA data transfer information.
    Block Diagram -- AXI4-Stream to/from AXI Memory Map – 2 DMA Channels - Control by SGL Descriptors
  • Peripheral Direct Memory Access Controller
    • AMBA AXI4-Lite slave bus
    • AMBA AXI4 master bus
    • Configurable number of peripheral channels
    • 8, 16, 32 bits data transfer modes
    Block Diagram -- Peripheral Direct Memory Access Controller
  • Peripheral Direct Memory Access Controller
    • AMBA APB3 slave bus
    • AMBA AHB-Lite master bus
    • Configurable number of peripheral channels
    • 8, 16, 32 bits data transfer modes
    Block Diagram -- Peripheral Direct Memory Access Controller
  • DMA Controller with TileLink IIP
    • Supports 1-16 channel DMA Transmit and DMA Receive Engine
    • Compliant with TileLink specification v1.7.1
    • Supports access for Ring and Chained Descriptor Structures
    • Configurable Transmit and Receive Engine based on Host Memory Data Width
    Block Diagram -- DMA Controller with TileLink IIP
  • DMA Controller with OCP IIP
    • Supports 1-16 channel DMA Transmit and DMA Receive Engine
    • Compliant with OCP 3.1 specification
    • Supports access for Ring and Chained Descriptor Structures
    • Configurable Transmit and Receive Engine based on Host Memory Data Width
    Block Diagram -- DMA Controller with OCP IIP
  • DMA Controller with AXI IIP
    • Supports 1-16 channel DMA Transmit and DMA Receive Engine
    • Supports latest ARM AMBA 3/4 AXI, AXI4-Lite, AMBA4 ACE, AMBA4 ACE-Lite, AXI4-Stream specification.
    • Supports access for Ring and Chained Descriptor Structures
    • Configurable Transmit and Receive Engine based on Host Memory Data Width
    Block Diagram -- DMA Controller with AXI IIP
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