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Spacewire IP

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Compare 7 Spacewire IP from 3 vendors (1 - 7)
  • SpaceWire CODEC
    • The GRSPW_CODEC core implements a SpaceWire encoder-decoder with a 9-bit wide FIFO host interface in each direction. The core complies to the SpaceWire standard (ECSS-E-ST-12C).
    • Data is transmitted and received through 9-bit wide FIFOs with configurable depth. The core also provides an interface for transmitting and receiving Time-codes as well as configuring the link properties such as the link rate.
    Block Diagram -- SpaceWire CODEC
  • SpaceWire Router
    • The SpaceWire router IP core supports all mandatory and optional features in the ECSS-E-ST-50-12C. It supports from 2 to 31 ports in addition to the mandatory configuration port.
    • Each port (except the configuration port) can be individually configured to be SpaceWire links, FIFO interfaces or AMBA interfaces.
    • The AMBA ports are limited to a maximum of 16 in a single router. The configuration port provides an RMAP target (ECSS-E-ST-50-52C), and an optional AMBA AHB slave interface, both used for accessing internal configuration and status registers. The SpaceWire Plug-and-Play (PnP) protocol can optionally be supported on the configuration port.
    Block Diagram -- SpaceWire Router
  • SpaceWire link controller with SpaceWire RMAP support and AMBA host interface
    • Full implementation of Spacewire standard
    • Protocol ID extension ECSS-E-50-12 part 2
    • Optional RMAP protocol draft C
    • AMBA AHB back-end with DMA
    Block Diagram -- SpaceWire link controller with SpaceWire RMAP support and AMBA host interface
  • SpaceWire Verification IP
    • Compliant with ECSS E‐ST‐50‐12C Standard.
    • Supports speeds between 2 Mb/s and 400 Mb/s.
    • Supports sending packets of information from a source node to a specified destination node.
    • Supports full-duplex point-to-point serial data communication links.
    Block Diagram -- SpaceWire Verification IP
  • SpaceFibre Verification IP
    • Compliant with SpaceFibre ECSS Draft F3 Specification.
    • Supports data rate up to 2 Gb/s.
    • Multilaning improves the data rate up to 20 Gb/s.
    • Supports full duplex point to point serial data communication links.
    Block Diagram -- SpaceFibre Verification IP
  • SpaceWire Synthesizable Transactor
    • Supports ECSS E‐ST‐50‐12C Standard
    • Supports speeds between 2 Mb/s and 400 Mb/s
    • Supports Full SpaceWire Functionality
    Block Diagram -- SpaceWire Synthesizable Transactor
  • SpaceWire Verification IP
    • Available in UVM, System Verilog.
    • Compliant to Specification ECSS-E-ST-50-12 C rev 1.
    • Supports speeds between 2Mb/s to 400Mb/s
    • Supports full duplex Serial data communication links
    Block Diagram -- SpaceWire Verification IP
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Semiconductor IP