IP Catalog > Multimedia IP

Multimedia IP

Multimedia IP cores are IP blocks used in the design of multimedia processing systems. These IP cores are typically developed to perform specific functions related to handling multimedia data, such as audio, video, graphics, and imaging. Multimedia IP cores can handle a variety of tasks, including:

  • Video Encoding/Decoding (Codec): IP cores that can compress or decompress video streams (e.g., H.264, HEVC, VP9).
  • Audio Encoding/Decoding: IP cores used to compress or decompress audio data (e.g., MP3, AAC).
  • Image Processing: IP cores for tasks like scaling, filtering, or converting images (e.g., resizing, color space conversion).
  • Graphics Processing: IP cores for rendering graphics, handling 2D or 3D graphics rendering, and processing graphic objects in video games, GUIs, or other visual applications.
  • Video Streaming: IP cores that manage real-time streaming of video data for playback or transmission.
  • Signal Processing: IP cores that process signals from sensors, cameras, microphones, etc., typically to filter, enhance, or interpret the data.
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Search (601)
Compare 601 Multimedia IP from 90 vendors (1 - 10)
  • LZ4/Snappy Data Decompressor
    • LZ4SNP-D is a custom hardware implementation of a lossless data decompression engine for the LZ4 and Snappy compression algorithms.
    • The core receives compressed files, automatically detects the LZ4 or Snappy format, and outputs the decompressed data.
    Block Diagram -- LZ4/Snappy Data Decompressor
  • JPEG encoder
    • Baseline JPEG compliant (ITU T.81), Motion JPEG
    • Up to 12 bits depth possible (default: 8 bit)
    • Super low latency (less than 1/10 of frame duration for rolling shutter cameras)
    • Lossy compression by default
    • Fully bit and cycle accurate co-simulation model available in Docker container
    Block Diagram -- JPEG encoder
  • Color Enhancement IP
    • The Color Enhancement IP modifies or emphasizes color by controlling Saturation/Luminance/Hue.
    • The Color Enhancement can only adjust the color & brightness of the specific area that user wants. Therefore, no change in other regions due to color adjustment of each area.
    Block Diagram -- Color Enhancement IP
  • E-Series GPU IP
    • E-Series GPU IP delivers fast and flexible parallel compute that scales from wearables to the cloud.
    • E-Series represents a new era of GPU IP with the introduction of a lot of dense, deeply integrated acceleration for power-efficient AI operations – up to 4x more than Imagination D-Series GPU IP.
    Block Diagram -- E-Series GPU IP
  • J.83abc/DVB-C Cable FEC Encoder
    • The CMS0017 J.83abc/DVB-C Cable FEC Encoder combines all of the channel coding and Forward Error Correction functions specified by DVB-C and by J83 - Annexes A B and C. However, it does not include the Root-Raised-Cosine filters required by these standards.
    • The CMS0017 includes functions for framing, scrambling, interleaving, Reed-Solomon coding, trellis coding, and QAM mapping. With the exception of the common interleaver block, two independent datapaths are required.
    Block Diagram -- J.83abc/DVB-C Cable FEC Encoder
  • ATSC 8-VSB modulator
    • The CMS0033 ATSC 8-VSB Modulator with integrated Channel Coder has been designed specifically to implement the 8-VSB requirements of the ATSC Digital Television Standard (A/53).
    • The core provides all the necessary processing steps to modulate a single transport stream into a complex I/Q signal for input to a pair of DACs, or a DDS up-conversion DAC such as the AD9857(or AD9957). Optionally, the output can be selected as an IF to supply a signal DAC.
    Block Diagram -- ATSC 8-VSB modulator
  • QOI Image Decompressor IP Core
    • This core implements the QOI lossless image compression algorithm decompressing QOI header-less files and producing RGB 24 bits pixels.
    • Simple, fully synchronous design with low gate count.
    Block Diagram -- QOI Image Decompressor IP Core
  • HDTV H.264/AVC Limited Baseline Video Decoder
    • The OL_H264LD core is a hardware implementation of the H.264 baseline video compression algorithm.
    • The core decodes a bitstream produced by the OLH264e encoder and produces a video stream up to the highest HDTV resolution.
    • Simple, fully synchronous design with low gate count.
    Block Diagram -- HDTV H.264/AVC Limited Baseline Video Decoder
  • HDTV H.264/AVC Baseline Video Encoder
    • Fully compatible with the ITU-T H.264 baseline specification.
    • Proven in FPGA : VGA (640x480) at 30 fps in VirtexII-4 demo board.
    • Profile level 4.1, can be decoded by Main Profile decoder.
    • Supports up to the highest HDTV video resolution (1920x1080 @ 30 fps progressive).
    Block Diagram -- HDTV H.264/AVC Baseline Video Encoder
  • Multi-Channel HDTV H.264/AVC Limited Baseline Video Decoder
    • The OL_H264MCLD core is a hardware implementation of the H.264 baseline video compression algorithm.
    • The core decodes a bitstream produced by the OLH264e encoder and produces a video stream up to the highest HDTV resolution.
    • Simple, fully synchronous design with low gate count.
    Block Diagram -- Multi-Channel HDTV H.264/AVC Limited Baseline Video Decoder
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