IP Catalog > Interface IP > Memory Controller/PHY IP > HBM IP

HBM IP

HBM IP (High Bandwidth Memory Interface) cores enable high-speed data transfer between processors and memory, providing a significant performance boost for memory-intensive applications. Supporting advanced memory technologies like HBM1, HBM2, and HBM2E, HBM IP cores deliver ultra-fast data access, low latency, and high bandwidth, making them ideal for applications such as high-performance computing (HPC), artificial intelligence (AI), gaming, and data centers.

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Compare 60 HBM IP from 12 vendors (1 - 10)
  • HBM4/3E Combo PHY & Controller
    • The fourth-generation and third-generation HBM (HBM4/3E) technology is outlined by the JESD238A standard (for HBM3E) and an upcoming specification (for HBM4)
    • These technologies feature 256-bit memory access per channel, with a 1024-bit input/output interface for HBM3E and up to a 2048-bit interface for HBM4
    Block Diagram -- HBM4/3E Combo PHY & Controller
  • HBM3 PHY IP at 7/6nm
    • Compliant with JEDEC JESD238 HBM3
    • DFI5.1-based interface with memory controller
    • Compliant with ESD requirements
    • Supports up to 16-bit independent and asynchronous channel
    Block Diagram -- HBM3 PHY IP at 7/6nm
  • Memory Controller
    • JEDEC GDDR6 standard JESD250B
    • Fast frequency switching
    • Flexible Configuration
    Block Diagram -- Memory Controller
  • HBM4 Memory Controller
    • Supports HBM4 memory devices
    • Supports all standard HBM4 channel densities (up to 32 Gb)
    • Supports up to 10 Gbps/pin
    • Refresh Management (RFM) support
    • Maximize memory bandwidth and minimizes latency via Look Ahead command processing
    • Integrated Reorder functionality
    Block Diagram -- HBM4 Memory Controller
  • HBM3E/3 Memory Controller
    • Supports HBM3E / HBM3 memory devices
    • Supports all standard HBM3 channel densities (up to 32 Gb)
    • Supports up to 9.6 Gbps/pin (HBM3E) or 8.4 Gbps/pin (HBM3)
    • Refresh Management (RFM) support
    • Maximizes memory bandwidth and minimizes latency via Look-Ahead command processing
    • Integrated Reorder functionality
    Block Diagram -- HBM3E/3 Memory Controller
  • HBM2/2E Memory Controller Core
    • Supports HBM2E and HBM2 devices
    • Supports all standard HBM2/2E channel densities (4, 6, 8, 12, 16, 24 Gb)
    • Supports data rates of up to 3.6 Gbps/pin
    • Can handle two pseudo-channels with one controller or independently with two controllers
    • Queue-based interface optimizes performance and throughput
    • Maximizes memory bandwidth and minimizes latency via Look-Ahead command processing
    Block Diagram -- HBM2/2E Memory Controller Core
  • TSMC CLN7FF HBM3 PHY
    • IGAHBMX03A is a HBM3 (High Bandwidth Memory) PHY IP compliant to the JEDEC HBM3 DRAM Specification Rev 0.95.
    • Built on TSMC 7nm process node, it supports data rate up to 7200 Mbps per data pin with DFI 1:4 clock frequency ratio (controller clock : WCK = 1:4).
    Block Diagram -- TSMC CLN7FF HBM3 PHY
  • Simulation VIP for HBM3
    • Speed (MHz)
    • Clock: 1800MHz; data rate: 7.2Gbps/pin
    • Mode Registers
    • All 16 mode registers are supported
    Block Diagram -- Simulation VIP for HBM3
  • Simulation VIP for HBM
    • Speed (MHz)
    • 1800MHz (3.6 Gbps/pin)
    • Device Density
    • Supports a wide range of device densities from 1Gb to 24Gb
    Block Diagram -- Simulation VIP for HBM
  • HBM3 Synthesizable Transactor
    • Supports 100% of HBM3 protocol draft JEDEC specification version 1.1.
    • Supports all the HBM3 commands as per the specs.
    • Supports programmable clock frequency of operation.
    • Support all types of timing and protocol violation detection.
    Block Diagram -- HBM3 Synthesizable Transactor
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