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CAVP-Validated Post-Quantum Cryptography
2025-11-28T12:34:00+00:00
RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI
2025-11-28T09:25:00+00:00
Exclude Smart in Functional Coverage
2025-11-27T12:40:00+00:00
The role of AI processor architecture in power consumption efficiency
2025-11-27T08:30:28+00:00
Evaluating the Side Channel Security of Post-Quantum Hardware IP
2025-11-27T07:09:41+00:00
A Golden Source As The Single Source Of Truth In HSI
2025-11-27T06:43:57+00:00
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ONFI 5.2: What’s new in Open NAND Flash Interface's latest 5.2 standard
2025-11-26T08:06:00+00:00
Qualitas Semiconductor Demonstrates Live of PCIe Gen 6.0 PHY and UCIe v2.0 Solutions at ICCAD 2025
2025-11-26T08:01:00+00:00
Adapting Foundation IP to Exceed 2 nm Power Efficiency in Next-Gen Hyperscale Compute Engines
2025-11-26T06:56:00+00:00
WAVE-N v2: Chips&Media’s Custom NPU Retains 16-bit FP for Superior Efficiency at High TOPS
2025-11-26T06:19:34+00:00
Quintauris releases RT-Europa, the first RISC-V Real-Time Platform for Automotive
2025-11-25T16:31:26+00:00
Towards a Formal Verification of Secure Vehicle Software Updates
2025-11-25T07:40:00+00:00
M31 Debuts at ICCAD 2025, Empowering the Next Generation of AI Chips with High-Performance, Low-Power IP
2025-11-25T07:06:48+00:00
Perceptia Begins Port of pPLL03 to Samsung 14nm Process Technology
2025-11-25T01:04:00+00:00
Smarter Silicon with Menta eFPGA and HW/SW Co-Design
2025-11-24T14:20:48+00:00
Pasteur’s Magic Quadrant in AI: The Fusion of Fundamental Research and Practical
2025-11-24T13:01:33+00:00
A New Era for Edge AI: Codasip’s Custom Vector Processor Drives the SYCLOPS Mission
2025-11-24T12:45:25+00:00
How Time Sensitive Networking powers the Software Defined Vehicle
2025-11-24T12:27:45+00:00
Vorion: A RISC-V GPU with Hardware-Accelerated 3D Gaussian Rendering and Training
2025-11-24T11:41:00+00:00
Fragmentation to Standardization: Evaluating RISC-V’s Path Across Data Centers, Automotive, and Security
2025-11-24T09:41:40+00:00
Powering Up Efficiency: A Deep Dive into CXL L0p and its Verification
2025-11-24T07:36:00+00:00
Spectral Design and Test Inc. and BAE Systems Announce Collaboration in RHBD Memory IP Development
2025-11-24T07:02:11+00:00
VSORA and GUC Partner on Jotunn8 Datacenter AI Inference Processor
2025-11-24T06:55:00+00:00
Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs
2025-11-21T18:15:14+00:00
Right Sizing AI for Embedded Applications
2025-11-21T07:36:12+00:00
How Alternate Geometry Processing Enables Better Multi-Core GPU Scaling
2025-11-20T16:17:00+00:00
Three Ethernet Design Challenges in Industrial Automation
2025-11-20T15:07:00+00:00
Mixel MIPI IP Integrated into Automotive Radar Processors Supporting Safety-critical Applications
2025-11-20T14:50:00+00:00