Semiconductor IP Intelligence
Follow new IP cores, vendor updates, expert perspectives and technical trends across SoC, ASIC and chiplet design — with direct paths from industry news to real semiconductor IP in the marketplace.
Featured
This article presents an automated, pre-silicon configuration and closed-loop initialization framework for Memory Controller verification. The proposed solution parses JEDEC timing and configuration...
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Expert perspectives
Read perspectives from IP providers, EDA experts and semiconductor specialists on design automation, IP integration, verification, architectures and emerging technologies.
Expert insight
By Alexandre Manuel and Julia Baucher
Expert insight
By Jim Shiely
Expert insight
By Ilan Sever
Marketplace
Find IP cores related to the technologies covered in Pulse. Semi IP Hub helps engineers discover semiconductor IP without turning users into sales leads by default.
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Establishes device identity, protects cryptographic keys, anchors Secure Boot
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Technical articles
By Federico Villani, ETH Zurich
By Wu Yang, Southern Methodist University
Videos
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16:12
Speaker: Chiawei Wang, Neal Liu
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15:48
Speaker: Kurtis Bowman (AMD)
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15:20
Speaker: Raja Koduri
From news to IP discovery
Explore IP cores, providers and categories across interface, security, compute, memory, analog, mixed-signal and chiplet-ready technologies.
Semi IP Hub Pulse brings together semiconductor IP industry news, expert perspectives, technical articles, blogs and videos for engineers, SoC architects, ASIC design teams and semiconductor decision-makers.
It helps users follow new IP cores, ecosystem partnerships, research papers, silicon design trends, security IP, interface IP, RISC-V, AI acceleration, chiplets, photonics, memory technologies and other topics shaping the semiconductor IP market.