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Search (80)
Compare 80 SPI IP from 22 vendors (1 - 10)
  • SPI Master DO-254 IP Core
    • The SPI Master IP Core implements an SPI Master fully compliant to the SPI Standard (Motorola’s M68H11 Reference Manual).
    • The Serial Peripheral Interface (SPI)  bus is a synchronous serial communication interface specification used for short distance communication, primarily in embedded systems.
    Block Diagram -- SPI Master DO-254 IP Core
  • SPI Slave DO-254 IP Core
    • The SPI Slave IP Core implements an SPI Slave fully compliant to the SPI Standard (Motorola’s M68H11 Reference Manual).
    • The Serial Peripheral Interface (SPI)  bus is a synchronous serial communication interface specification used for short distance communication, primarily in embedded systems.
    Block Diagram -- SPI Slave DO-254 IP Core
  • Expanded Serial Peripheral Interface (xSPI) Slave Controller
    • The JESD251 Expanded Serial Peripheral Interface Slave controller is provides high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface(SPI) devices
    • It is used to connect xSPI Master devices in computing, automotive, Internet of Things, Embedded system and mobile system processor to non-volatile memories, graphics peripherals, networking peripherals,FPGAs, sensors devices
    Block Diagram -- Expanded Serial Peripheral Interface (xSPI) Slave Controller
  • Expanded Serial Peripheral Interface (xSPI)Master Controller
    • The Expanded Serial Peripheral Interface (JESD251) Master controller is low signal count, high data bandwidth, primarily for use in computing, automotive, Internet of Things, Embedded system and mobile system processor to connect multiple source of Serial Peripheral Interface (xSPI) slave devices like non-volatile memories, graphics peripherals, networking peripherals,FPGAs, sensors devices
    Block Diagram -- Expanded Serial Peripheral Interface (xSPI)Master Controller
  • SPI/BOSCH Verification IP
    • Follows SERIAL_FLASH basic specification as defined in Bosch SMB380 Triaxial acceleration sensor
    • Support Master and Slave Mode
    • Supports data width of 8 bit
    • Supports 3-wire,4-wire interface
    Block Diagram -- SPI/BOSCH Verification IP
  • SPI Slave IP transfers to/from a AMBA APB, AXI, or AHB Interconnect
    • The DB-SPI-S-AMBA-BRIDGE is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting only Slave SPI Bus transfers (both Full Duplex and Half Duplex) to/from a AMBA APB, AXI, or AHB Interconnect.
    • The DB-SPI-S-AMBA-BRIDGE contains dual clock Transmit/Receive FIFOs and Finite State Machine control to process incoming SPI transmit/receive transactions, and a AMBA Master Interface (i.e. APB, AXI, AHB5) to read or write the SPI payload data with respect to the AMBA Interconnect. No processor is required for configuration or control; the DB-SPI-S-AMBA-BRIDGE operates autonomously from reset.
    Block Diagram -- SPI Slave IP transfers to/from a AMBA APB, AXI, or AHB Interconnect
  • SPI Controller IP- Master/ Slave, Parameterized FIFO, Avalon Bus
    • The Digital Blocks DB-SPI-MS-AVLN is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers.
    • The DB-SPI-MS contains an Avalon Bus Interface for interfacing a microprocessor to external SPI Master/Slave devices.
    Block Diagram -- SPI Controller IP- Master/ Slave, Parameterized FIFO, Avalon Bus
  • Enhanced SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus. Supports eSPI Master & Slave and SPI Master & Slave functions
    • The DB-eSPI-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI) bus transfers to the standard SPI Master/Slave Controller. The DB-eSPI-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external eSPI or SPI Master/Slave devices.
    • The DB-eSPI-SPI-MS contains both eSPI and SPI Master and Slave functions.
    Block Diagram -- Enhanced SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus. Supports eSPI Master & Slave and SPI Master & Slave functions
  • SPI Controller IP- Master-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus
    • The DB-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and Half Duplex).
    • The DB-SPI-M contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external SPI Slave devices.
    Block Diagram -- SPI Controller IP- Master-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus
  • SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus
    • The DB-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external SPI Master/Slave devices.
    • The DB-SPI-MS contains Transmit/Receive FIFOs and Finite State Machine control with status & interrupt capability to fully off-load from the microprocessor the transfer of data over the SPI Bus. Optionally, the user can transfer transmitted or received data from the SPI Bus to user memory via an optional DMA Controller.
    Block Diagram -- SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus
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