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Search (75)
Compare 75 SPI IP from 20 vendors (1 - 10)
  • Enhanced SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus. Supports eSPI Master & Slave and SPI Master & Slave functions
    • The DB-eSPI-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI) bus transfers to the standard SPI Master/Slave Controller. The DB-eSPI-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external eSPI or SPI Master/Slave devices.
    • The DB-eSPI-SPI-MS contains both eSPI and SPI Master and Slave functions.
    Block Diagram -- Enhanced SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus. Supports eSPI Master & Slave and SPI Master & Slave functions
  • SPI Serial Peripheral Interface Master/Slave
    • SPI-compatible interface
    • AMBA AXI4-Lite bus
    • Master or slave mode
    • Full duplex
    Block Diagram -- SPI Serial Peripheral Interface Master/Slave
  • SPI Serial Peripheral Interface Master/Slave
    • SPI-compatible interface
    • AMBA APB3 bus
    • Master or slave mode
    • Full duplex
    Block Diagram -- SPI Serial Peripheral Interface Master/Slave
  • Serial Peripherial Interface
    • Provides AXI interface
    • Provides Interface to DMA
    • Provides direct PIO access to SPI flash devices for BIOS boot up
    Block Diagram -- Serial Peripherial Interface
  • Simulation VIP for xSPI
    • xSPI Profile 1
    • SPI (Read Zero Latency), DUAL (1-1-2, 1-2-2), Quad (As per JESD251-A1), and Octal modes Data Rate: STR and DTR
    • Modes
    • SPI-STR (1S-1S-1S), QUAD-STR (4S-4S-4S), OCTAL-STR(8S-8S-8S), and OCTAL-DTR (8D-8D-8D) modes
    Block Diagram -- Simulation VIP for xSPI
  • Simulation VIP for SPI
    • Full Duplex
    • Simultaneous transfer from Manager and Subordinate
    • Variable Size Shift Registers
    • 8, 16, and 32-bit shift register for Tx and Rx
    Block Diagram -- Simulation VIP for SPI
  • Simulation VIP for Q-SPI
    • Device Density
    • From 256Mb to 2Gb with frequency up to 166MHz
    • Operation Mode
    • Single I/O, Dual I/O, and Quad I/O (Q-SPI and QSPI) with single and double transfer rate (STR and DTR)
    Block Diagram -- Simulation VIP for Q-SPI
  • SPI to AHB-Lite Bridge
    • The SPI2AHB core implements an SPI slave to AHB-Lite master bridge. It allows an external SPI master to perform read or write access to any memory-mapped device on the internal AHB bus.
    • The core implements a simple over-SPI protocol to convert SPI transactions into AHB Read or Write instructions.
    Block Diagram -- SPI to AHB-Lite Bridge
  • Octal SPI Master/Slave Controller
    • Implements a controller for a single-, dual-, quad-, or octal-lane Serial Peripheral Interface (SPI) bus, which can operate either as a master or as a slave. 
    • Designed to work with a wide variety of SPI bus variants, the core supports run-time control of several SPI protocol parameters.
    Block Diagram -- Octal SPI Master/Slave Controller
  • I2C and SPI Master/Slave Controller
    • The I2CSPI-CTRL is a compact and versatile serial interface controller supporting both SPI (Serial Peripheral Interface) and I2C (Inter-Integrated Circuit) protocols.
    • Its low silicon resource requirement makes it suitable for area-constrained and low-power applications, while its software compatibility with Microchip’s MSSP peripheral eases use and software integration.
    Block Diagram -- I2C and SPI Master/Slave Controller
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