SPI IP

Welcome to the ultimate SPI IP hub! Explore our vast directory of SPI IP
All offers in SPI IP
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Compare 54 SPI IP from 18 vendors (1 - 10)
  • SPI Serial Peripheral Interface Master/Slave
    • SPI-compatible interface
    • AMBA AXI4-Lite bus
    • Master or slave mode
    • Full duplex
    Block Diagram -- SPI Serial Peripheral Interface Master/Slave
  • SPI Serial Peripheral Interface Master/Slave
    • SPI-compatible interface
    • AMBA APB3 bus
    • Master or slave mode
    • Full duplex
    Block Diagram -- SPI Serial Peripheral Interface Master/Slave
  • SPI Master / Slave Controller w/FIFO (APB Bus)
    • Master and Slave SPI Modes
    • Full Duplex Transfers – Simultaneous Transmit & Receive
    • Four Signal Interface:
    • Up to N=8 Slave Select (SS) Outputs for multiple Slaves on SPI Bus
    Block Diagram -- SPI Master / Slave Controller w/FIFO (APB Bus)
  • Serial Peripherial Interface
    • Provides AXI interface
    • Provides Interface to DMA
    • Provides direct PIO access to SPI flash devices for BIOS boot up
    Block Diagram -- Serial Peripherial Interface
  • eSPI Synthesizable Transactor
    • Compliant with eSPI base specification as defined in Enhanced Serial Peripheral Interface (eSPI) Specification rev.1.0
    • Supports addendum 0.7
    • Supports Master and Slave Modes
    • Supports Single, Dual and Quad modes
    Block Diagram -- eSPI Synthesizable Transactor
  • XSPI Master IIP
    • Compliant with XSPI protocol of JEDEC standard version 1.0 specification
    • Support single master and multiple slaves per interface port
    • Support source synchronous clocking
    • Support Deep power down enter and exit commands
    Block Diagram -- XSPI Master IIP
  • XSPI Controller IIP
    • Compliant with XSPI protocol of JEDEC standard version 1.0 specification
    • Support single master and multiple slaves per interface port
    • Support source synchronous clocking
    • Support Deep power down enter and exit commands
    Block Diagram -- XSPI Controller IIP
  • SPI Slave To SOC Bridge IIP
    • Compliant with the SPI Block Guide 4.01 standard.
    • Full SPI Slave functionality.
    • Converts SPI Transactions into SOC write or read access.
    • Allows external devices to access the internal SOC Bus
    Block Diagram -- SPI Slave To SOC Bridge IIP
  • SPI Slave IIP
    • Compliant with SPI Block Guide 4.01 Specification.
    • Full SPI Slave functionality.
    • Supports flexible transfer format to work with slower interfaces
    • Supports Single, Dual, Quad, Octal data widths
    Block Diagram -- SPI Slave IIP
  • SPI Master IIP
    • Compliant with SPI Block Guide 4.01 Standard
    • Complaint to TI and National Modes (Microwire)
    • Supports 3 wire and 4 wire operation
    • Supports DDR mode of operation
    Block Diagram -- SPI Master IIP
×
Semiconductor IP