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Compare 15 SPI IP from 11 vendors (1 - 10)

SPI Slave Serial Interface Controller
- The SPI_SLAVE IP Core is an SPI compliant slave interface controller. The controller decodes the bus signals and de-serializes them into a series of 8-bit bytes.
- Communication with the slave controller is achieved by programming a single control register and a single address register.
SPI Controller IP- Master-only, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- The DB-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and Half Duplex).
- The DB-SPI-M contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external SPI Slave devices.
SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- The DB-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS contains an AMBA AXI, AHB, or APB Bus Interface for interfacing a microprocessor to external SPI Master/Slave devices.
- The DB-SPI-MS contains Transmit/Receive FIFOs and Finite State Machine control with status & interrupt capability to fully off-load from the microprocessor the transfer of data over the SPI Bus. Optionally, the user can transfer transmitted or received data from the SPI Bus to user memory via an optional DMA Controller.
QSPI FLASH Controller – XIP functionality (SINGLE, DUAL and QUAD SPI Bus Controller with Double Data Rate support)
- Set of software accessible control registers to execute any Flash memory command
- Supports any device clock frequency, polarity and phase,
- Programmable baud rate generator,
- Built in FLASH Commands decoder supports most popular FLASH devices,
Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support
- Operates with 8, 16 and 32 bit CPUs
- Full duplex synchronous serial data transfer
- DMA support
- Support for 32, 16 and 8 bit systems
SPI4.2
- The Soft SPI4 IP core is fully compliant with the OIF System Packet Interface Level 4 Phase 2 Revision 1 (SPI4.2.1) interface standard
- Supported through Diamond or ispLEVER IPexpress™ tool for easy user configuration and parameterization
- Supports up to 256 independent channels
- 400 to 500MHz DDR Dynamic mode operation in LatticeSC and LatticeSCM devices
SPI to AMBA AHB Master Bridge
- Serial SPI Compatible
- Low Pin Count Interface (4 pins)
- Can be shared with other chip I/O functions
SPI to AXI4 Controller Bridge
- Try Before Buy - No cost and no obligation!
- Supports Xilinx® ZynqTM-7000 AP SoC and all Xilinx FPGAs
- Bridge controller between the serial SPI bus and the parallel AXI4 bus
- Works as a Slave controller on the SPI bus
Serial Peripheral Interface - Master/Slave
- SPI Master
- SPI Slave
- Available system interface wrappers:
- Fully synthesizable
Serial Peripheral Interface - Master/Slave with single, dual and quad SPI Bus support
- Operates with 8, 16 and 32 bit CPUs
- Full duplex synchronous serial data transfer
- DMA support
- Support for 32, 16 and 8 bit systems