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VESA DSC IP

Welcome to the ultimate VESA DSC IP hub! Explore our vast directory of VESA DSC IP Cores

VESA DSC IP cores provide a low-latency, low-complexity codec specifically designed for data compression over the display interface.

VESA Display Compression Codecs (DSC) IP cores can compress any image to 8 bits per pixel (bpp), which results in a 3X compression ratio for a 24 bpp image or a 3.75X compression ratio for a 30 bpp image.

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Compare 28 VESA DSC IP from 10 vendors (1 - 10)
  • VESA DSC V1.2 Encoder
    • VESA introduced the first Display Stream Compression (DSC) standard in 2014. The DSC 1.1 has been incorporated into the VESA Embedded DisplayPort (eDP) and MIPI® DSI embedded mobile interface standards. The latest VESA Display Compression-M (VDC-M) standard has also been adopted into the MIPI DSI standard. For mobile applications, DSC 1.1 and VDC-M mainly serve to reduce the video interface data rate, which reduces system power, prolongs battery life, and reduces interconnects to enable sleeker designs. For external display interfaces, DSC 1.2b extends resolution across existing connectors and cables, enabling 8K video and legacy support from the same connection.
    • Being compliant with the VESA DSC 1.2a and 1.2b standards, the IP core supports various prediction schemes (MMAP, BP, MPP, ICH) as well as color formats in YCbCr and RGB. It transfers more pixel data over display links to save memory size in embedded frame buffers in display driver ICs and performs visually lossless compression, low gate count and latency for ultra-high-definition display applications. It can be easily integrated into ASIC and FPGA applications.
    • Programmable display resolutions
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    Block Diagram -- VESA DSC V1.2 Encoder
  • VESA DSC V1.2 Decoder
    • Being compliant with the VESA DSC 1.2a and 1.2b standards, the IP core supports various prediction schemes (MMAP, BP, MPP, ICH) as well as color formats in YCbCr and RGB.
    • It transfers more pixel data over display links to save memory size in embedded frame buffers in display driver ICs and performs visually lossless compression, low gate count and latency for ultra-high-definition display applications.
    Block Diagram -- VESA DSC V1.2 Decoder
  • VESA DSC V1.2 Encoder
    • Being compliant with the VESA DSC 1.2a and 1.2b standards, the IP core supports various prediction schemes (MMAP, BP, MPP, ICH) as well as color formats in YCbCr and RGB.
    • It transfers more pixel data over display links to save memory size in embedded frame buffers in display driver ICs and performs visually lossless compression, low gate count and latency for ultra-high-definition display applications. It can be easily integrated into ASIC and FPGA applications.
    Block Diagram -- VESA DSC V1.2 Encoder
  • VESA DSC V1.2 Decoder
    • Being compliant with the VESA DSC 1.2a and 1.2b standards, the IP core supports various prediction schemes (MMAP, BP, MPP, ICH) as well as color formats in YCbCr and RGB.
    • It transfers more pixel data over display links to save memory size in embedded frame buffers in display driver ICs and performs visually lossless compression, low gate count and latency for ultra-high-definition display applications. It can be easily integrated into ASIC and FPGA applications.
    Block Diagram -- VESA DSC V1.2 Decoder
  • Display Stream Compression (DSC 1.2) Encoder
    • The Display Stream Compression (DSC) Encoder offers real-time compression of high-definition streams with resolutions up to 8K.
    • The core supports 8, 10, 12, 14 or 16 bits per pixel input using either RGB or YCbCr in 4:4:4 or 4:2:2 format.
    • The DSC Encoder core integrates industry standard interfaces for host configuration and control, video input, and output.
    Block Diagram -- Display Stream Compression (DSC 1.2) Encoder
  • Display Stream Compression (DSC 1.2) Decoder
    • The Display Stream Compression (DSC) Decoder core offers realtime decompression of high-definition streams with resolutions from 480 to 8K.
    • The core supports 8, 10, 12, 14 or 16 bits per pixel using either RGB or YCbCr in 4:4:4 or 4:2:2 format.
    • The DSC Decoder core integrates industry standard interfaces for host configuration and control, data input, and video output.
    Block Diagram -- Display Stream Compression (DSC 1.2) Decoder
  • Scalable Ultra-High Throughput VESA DSC 1.2b Decoder
    • The UHT-DSC-D core is a scalable, ultra-high throughput, advanced DSC 1.2b decoder, compliant to the VESA Display Stream Compression (DSC) 1.2b standard.
    • It supports decoding of 4:4:4, 4:2:2 and 4:2:0 video streams, in 8 to 16 bits per component color depths.
    • The core is designed for enabling ultra-high frame rate SD, HD and Ultra HD video decoding up to 10K resolutions, even in medium-end ASIC or FPGA silicon.
    Block Diagram -- Scalable Ultra-High Throughput VESA DSC 1.2b Decoder
  • Scalable Ultra-High Throughput VESA DSC 1.2b Encoder
    • The UHT-DSC-E core is an advanced video encoder IP, compliant to the VESA Display Stream Compression (DSC) v1.2b standard.
    • It supports encoding of 4:4:4, 4:2:2 and 4:2:0 video streams, in 8 to 16 bits sample depths.
    • The core is scalable and has been designed for enabling ultra-high throughput video encoding, even in medium-range target implementation technologies.
    Block Diagram -- Scalable Ultra-High Throughput VESA DSC 1.2b Encoder
  • DisplayPort 1.4 FEC Receiver (Rx)
    • VESA DisplayPort 1.4 compliant
    • Reed-Solomon RS (254,250) FEC, 10-bit symbols
    • Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
    • DisplayPort main 8b/10b encoder included (Tx only)
    • Status and control can be done with signals or optionally via an integrated APB register module (Rx)
    Block Diagram -- DisplayPort 1.4 FEC Receiver (Rx)
  • VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
    • VESA DisplayPort 1.4 compliant
    • Reed-Solomon RS (254,250) FEC, 10-bit symbols
    • Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
    • DisplayPort main 8b/10b encoder included (Tx only)
    • Status and control can be done with signals or optionally via an integrated APB register module (Rx)
    Block Diagram -- VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
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