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This controller supports AP Memory’s Xccela open standard Bus for digital interconnect and data communications, suitable for non-volatile and volatile memories such as PSRAM.
This controller enables smooth integration AP memory’s of Xccela PSRAM memory chips into various new-gen devices made with mobile and wearable low power SoCs’.
This memory controller implementation is designed to give the user full flexibility for driving the memory control signals and timing adjustment for data sampling.

Compatible with spansion hyperbus based memory products.
0 Wait State Write Burst Operation for HyperBus memory on AXI interface of up to 256 words.

The AHB Parallel Flash Controller allows an AHB Master component (usually a CPU) to read, program, or erase the connected arrangement of external parallel SuperFlash devices.
The controller implements a set of configuration registers on an APB interface, while Flash accesses occur via an AHB interface. It also implements several modes of operation to facilitate these functions.

The AHB SRAM Controller provides a standard AHB interface to translate AHB bus reads and writes into reads and writes with the signaling and timing of a standard 32-bit synchronous SRAM.
The AHB SRAM Controller provides zero-wait-state AHB access to the synchronous SRAM in all cases except for the following back-toback events: an AHB write directly followed by an AHB read.

The xSPI-MC core is a versatile serial/SPI memory controller, which allows a system to easily detect and access the attached memory device or directly boot from it.
The controller core supports most of the proprietary SPI protocols used by Flash and PSRAM device vendors and is compatible to JEDEC’s eXpanded SPI (xSPI), HyperBus™ and Xccela™ standards.