The Semiconductor IP Marketplace

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Spotlight

  • Analog I/O Library with a custom 12V ESD Solution IN GF 55nm
    • This I/O library is a silicon-proven, flip-chip-optimized analog and mixed-signal I/O Library for GlobalFoundries 55nm BCD technology.
    • It provides a comprehensive set of 1.8V, 3.3V, 5V, and 12V analog I/O and power pads, designed for robust ESD protection, flexible pad-ring construction, and reliable operation across industrial temperature ranges.
  • JESD204E Controller IP
    • The JESD204E Controller IP from Chip Interfaces is an early adopter’s version of the upcoming revision of the JEDEC standard for Serial Interface for Data Converters.
    • The JESD204-E IP core supports the UCIe Optimized Link Layer, a dedicated mode to run JESD over UCIe Modules with Line rates up the 64Gbps per bump, and a JESD204D backwards compatible mode called the Unified Link Layer with line speeds up to 116Gbps with PAM4 and 58Gbps with NRZ and full FEC support.
    Block Diagram -- JESD204E Controller IP
  • HPC MACsec Security Modules for Ethernet
    • IEEE 802.1ae, IEEE 802.1br Support
    • 100 Gbps—1.6 Tbps
    • Can reach higher throughputs scalable to 3.2 Tbps
    • Supports also lower performance modes down to 10 Gbps
  • eUSB2V1.2 Controller + PHY IP
    • eUSB2 can support USB high-speed, full-speed, and low-speed operation, as well as the USB 2.0 L1/L2 link power management requirements. In addition, eUSB2 requires no change to the existing USB 2.0 software programming model.
    • eUSB2 also uses the same two data line configurations, eD+ and eD- as USB2 D+ and D-. Vbus and power delivery are not impacted by eUSB2.
    Block Diagram -- eUSB2V1.2 Controller + PHY IP
  • Standard Cell Library in SkyWater 90nm
    • This Standard Cell Library is a production-ready, low-leakage digital logic library developed for the SkyWater 90nm (S90 / C9) process.
    • Built on a proven standard cell architecture, the library provides comprehensive combinational, sequential, clocking, and power-management cells optimized for reduced standby power, predictable PPA, and robust SoC integration.
  • RISC-V IOPMP IP
    • The I/O Physical Memory Protection (IOPMP) unit is a hardware-based access control mechanism designed to safeguard memory regions in RISC-V SoCs.
    • It ensures only authorized devices and masters can access sensitive memory areas, enabling secure and reliable system operation.
    Block Diagram -- RISC-V IOPMP IP

UCIe Controller IP View All

  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • TSMC CLN5FF GUCIe LP Die-to-Die PHY
    • IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
    • This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the
    Block Diagram -- TSMC CLN5FF GUCIe LP Die-to-Die PHY

PCIe 7.0 IP View All

  • PCIe 7.0 Controller with AXI
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Separate native TX/RX data path separating posted/Non posted/completion traffic
    • Handles up to 4 TLPs per cycle
    • Advanced PIPE modes and port bifurcation
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
  • PCIe 7.0 PHY in TSMC (N5, N3P)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SSC)

AI IP View All

  • RISC-V CPU IP
    • RISC-V RVA23 Compliant 
    • >18 SPECint2006/GHz
    • 8-wide decode unit
    • Advanced branch predictor
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
    • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
    • Future proof architecture that supports the most advanced ML data types and operators
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    • RISC-V-based AI IP development for enhanced training and inference.
    • Silicon-proven solutions tailored for AI workload optimization.
    • Energy-efficient performance with industry-leading Perf/W.
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar

MIPI IP View All

RISC-V IP View All

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