The Semiconductor IP Marketplace

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The Semiconductor IP Marketplace that puts you first

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Spotlight

  • KYBER IP Core
    • supports encapsulation and decapsulation operations
    • supports all modes K=2,3,4.
    • is compliant with Kyber specification round 3.
    • has fully stallable input and output interfaces. 
    • Key generation feature is going to be implemented in the near future.
    Block Diagram -- KYBER IP Core
  • True Random Number Generator (TRNG) IP
    • The TRNG IP delivers NIST- and BSI-compliant entropy for secure embedded and SoC designs.
    • With robust health testing and digital or analog implementation options, our TRNGs provide the foundation for trusted key generation, encryption, and authentication in mission-critical applications.
  • Highly-optimized PQC implementations, capable of running PQC in under 15kb RAM
    • PQCryptoLib-Emebedded is a versatile, CAVP-ready cryptography library designed and optimized for embedded devices.
    • With its design focused on ultra-small memory footprint, PQCryptoLib-Embedded solutions have been specically designed for embedded systems, microcontrollers and memory-constrained devices. It provides a PQC integration to devices already in the field.
    Block Diagram -- Highly-optimized PQC implementations, capable of running PQC in under 15kb RAM
  • Audio Sample Rate Converter
    • The ASRC core is a compact and high-performance audio sample rate converter.
    • It accurately converts digital audio signals between different sample rates while maintaining signal integrity and minimizing distortion.
    • Supporting both asynchronous and synchronous conversion modes, the low latency ASRC can be used in real-time streaming applications as well as in high-speed batch processing environments.
    Block Diagram -- Audio Sample Rate Converter
  • Cryptographic Cores IP
    • The Cryptographic Cores IP portfolio delivers secure, high-performance implementations of symmetric, asymmetric, and post-quantum algorithms.
    • Designed for low-area, low-latency operation, the silicon-proven cores help SoC designers and embedded teams build trusted, efficient devices for IoT, automotive, medical, and industrial markets.
  • DVB-S2X Wideband LDPC/ BCH Encoder
    • Compliant with ETSI EN 302 307’
    • Compliant with ETSI EN 302 307-2’
    • Supports BCH-LDPC all code rates for digital video broadcasting

UCIe Controller IP View All

  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
    • High Bandwidth Density and Data Rates
    • Package Configurability
    • Energy Efficiency
    • Fully Integrated Solution
    Block Diagram -- 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe

PCIe 7.0 IP View All

  • PCIe 7.0 Controller with AXI
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Separate native TX/RX data path separating posted/Non posted/completion traffic
    • Handles up to 4 TLPs per cycle
    • Advanced PIPE modes and port bifurcation
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
  • PCIe 7.0 PHY in TSMC (N5, N3P)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SSC)

AI IP View All

  • RISC-V CPU IP
    • RISC-V RVA23 Compliant 
    • >18 SPECint2006/GHz
    • 8-wide decode unit
    • Advanced branch predictor
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
    • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
    • Future proof architecture that supports the most advanced ML data types and operators
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    • RISC-V-based AI IP development for enhanced training and inference.
    • Silicon-proven solutions tailored for AI workload optimization.
    • Energy-efficient performance with industry-leading Perf/W.
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar

MIPI IP View All

RISC-V IP View All

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