The Semiconductor IP Marketplace

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Spotlight

  • Low Dropout (LDO) Regulator
    • Input voltage of 1.8V
    • Output voltage of 1.35V
    • Up to 100mA output current.
    • Stable with Off-chip capacitor 1uF
    Block Diagram -- Low Dropout (LDO) Regulator
  • 16-Bit xSPI PSRAM PHY
    • Supports for both the xSPI and PSRAM Master host controller IPs.
    • Support 500Mbps per line along with the high speed xSPI modes > 50MHz.
    Block Diagram -- 16-Bit xSPI PSRAM PHY
  • ASIL B Compliant MIPI CSI-2 CSE2 Security Module
    • Supports MIPI - Camera Service Extensions CSE 2.0 specification
    • Automotive‑ compliant: ISO 26262 (ASIL‑B) & ISO 21434
    • Plug‑and‑play with Synopsys CSI‑2 Host Controllers
    • Data integrity protection and optional encryption (AES-CMAC, AES-GMAC, AES-CTR)
  • SHA-256 Secure Hash Algorithm IP Core
    • Supports SHA-256 cryptographic algorithm, an one-way hash function compliant to NIST’s FIPS 180-4 standard.
    Block Diagram -- SHA-256 Secure Hash Algorithm IP Core
  • 5 GHz 150 fs Jitter PLL - GlobalFoundries 22nm
    • Input Frequency: ~100MHz, ~200MHz
    • Output Frequency: 5 GHz
    • RMS Jitter: <150 fs
    • Supply Voltages: 0.8 V, 1.8V 
  • EdDSA Curve25519 signature generation engine
    • The EdDSA Curve25519 extension adds hardware support for modern elliptic-curve cryptography inside DCD-SEMI’s configurable cryptographic co-processor.
    • The implementation is based on Curve25519, a widely adopted 255-bit elliptic curve designed for efficient key exchange and digital signatures, with strong resistance to side-channel attacks and high performance in constrained embedded environments.
    Block Diagram -- EdDSA Curve25519 signature generation engine

UCIe Controller IP View All

  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • TSMC CLN5FF GUCIe LP Die-to-Die PHY
    • IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
    • This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the
    Block Diagram -- TSMC CLN5FF GUCIe LP Die-to-Die PHY

PCIe 7.0 IP View All

  • PCIe 7.0 Controller with AXI
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Separate native TX/RX data path separating posted/Non posted/completion traffic
    • Handles up to 4 TLPs per cycle
    • Advanced PIPE modes and port bifurcation
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
  • PCIe 7.0 PHY in TSMC (N5, N3P)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SSC)

AI IP View All

  • RISC-V CPU IP
    • RISC-V RVA23 Compliant 
    • >18 SPECint2006/GHz
    • 8-wide decode unit
    • Advanced branch predictor
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
    • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
    • Future proof architecture that supports the most advanced ML data types and operators
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    • RISC-V-based AI IP development for enhanced training and inference.
    • Silicon-proven solutions tailored for AI workload optimization.
    • Energy-efficient performance with industry-leading Perf/W.
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar

MIPI IP View All

RISC-V IP View All

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