The Semiconductor IP Marketplace

Try an example: PCIe 7.0
☰ Semiconductor IP

The Pulse

The Semiconductor IP Marketplace that puts you first

Semi IP Hub's mission is to provide you with a platform where you can find Silicon IP cores for your next project without being harassed by dozens of sellers.

Here, your contact details are not shared with third parties unless you request to be contacted by a supplier.

Spotlight

  • UCIe PHY (Die-to-Die) IP
    • Compliant with UCIe v2.0, supporting 4/8/12/16/24/32GT/s data rates
    • for Standard Package up to 16 lanes / for Advanced Package up to 64 lanes
    • Provides a 1024-bit data bus width with high-throughput die-to-die communication
    • Includes automatic per-lane calibration and optional transmitter de-emphasis
    Block Diagram -- UCIe PHY (Die-to-Die) IP
  • Simulation VIP for LPDDR6
    • This Verification IP (VIP) is intended for modeling the upcoming JEDEC Low-Power Memory Device, LPDDR6 design specification.
    • It provides a mature, highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification.
    Block Diagram -- Simulation VIP for LPDDR6
  • UCIe-S 64GT/s PHY IP
    • The UCIe-S 64GT/s PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-high-speed interconnects between dies in standard packaging environments.
    • Leveraging the UCIe (Universal Chiplet Interconnect Express) 3.0 standard, this IP supports a blistering data rate of up to 64Gbps per lane, enabling next-generation AI, HPC, and data center SoC applications.
  • UA Link DL IP core
    • The UA Link DL IP Core is a high-performance, silicon-agnostic and fully compliant Data Layer implementation of UALink_200 specifi cation.
    • Designed for seamless integration into accelerator, switch, and SoC designs, it delivers deterministic low-latency, robust error correction, and compatibility with multiple high-speed Ethernet-derived link rates.
    Block Diagram -- UA Link DL IP core
  • 10-bit Pipeline ADC - Tower 180 nm
    • 10-bit resolution
    • 25 MSPS sampling rate
    • 6 mW power
    • 25 MHz Input Bandwidth
  • NoC Verification IP
    • Complex network with acyclic agent graph (DAG). Layered and parallel NOC is also supported.
    • Any number of master and slave ports is supported. Each port can be configured individually.
    • ARM® AHB3-Lite,5, ARM® AXI 3,4,4-Lite,5,5-Lite, ARM® APB 2,3,4,5, SiFive TileLink Tl-UL, Tl-UH, TL-C.
    Block Diagram -- NoC Verification IP

UCIe Controller IP View All

  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • TSMC CLN5FF GUCIe LP Die-to-Die PHY
    • IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
    • This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the
    Block Diagram -- TSMC CLN5FF GUCIe LP Die-to-Die PHY

PCIe 7.0 IP View All

  • PCIe 7.0 Controller with AXI
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Separate native TX/RX data path separating posted/Non posted/completion traffic
    • Handles up to 4 TLPs per cycle
    • Advanced PIPE modes and port bifurcation
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
  • PCIe 7.0 PHY in TSMC (N5, N3P)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SSC)

AI IP View All

  • RISC-V CPU IP
    • RISC-V RVA23 Compliant 
    • >18 SPECint2006/GHz
    • 8-wide decode unit
    • Advanced branch predictor
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
    • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
    • Future proof architecture that supports the most advanced ML data types and operators
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    • RISC-V-based AI IP development for enhanced training and inference.
    • Silicon-proven solutions tailored for AI workload optimization.
    • Energy-efficient performance with industry-leading Perf/W.
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar

MIPI IP View All

RISC-V IP View All

×
Semiconductor IP