The Pulse
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IC’Alps joins Intel Foundry Accelerator program as Value Chain Alliance (VCA) and Design Services Alliance (DSA) partner
2025-04-30T12:55:00+02:00
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Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
2025-04-30T12:25:00+02:00
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TSMC shuns high-NA EUV lithography
2025-04-30T09:39:00+02:00
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SkyeChip Joins Intel Foundry Accelerator IP Alliance
2025-04-30T08:42:00+02:00
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Weebit Nano Q3 FY25 Quarterly Activities Report
2025-04-30T07:30:00+02:00
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Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
2025-04-29T19:41:00+02:00
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Intel Foundry Gathers Customers and Partners, Outlines Priorities
2025-04-29T19:24:00+02:00
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Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
2025-04-29T17:43:00+02:00
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Scaling AI Infrastructure with Next-Gen Interconnects
2025-04-29T16:22:00+02:00
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VSORA Raises $46 Million to Bring World’s Most Powerful AI Inference Chip to Market
2025-04-29T15:51:00+02:00
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Worldwide Silicon Wafer Shipments Increase 2% Year-on-Year in Q1 2025
2025-04-29T15:06:00+02:00
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xMEMS Extends µCooling Fan-on-a-Chip Technology to AI Data Centers
2025-04-29T14:49:00+02:00
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Codasip launches complete exploration platform to accelerate CHERI adoption
2025-04-29T14:02:00+02:00
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eMMC: The Embedded Storage Powering On-Device AI
2025-04-29T13:10:00+02:00
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GPIO Solutions for CERN’s Radiation-Hardened Applications
2025-04-29T12:44:00+02:00
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Imec coordinates EU Chips Design Platform
2025-04-29T12:36:00+02:00
The Semiconductor IP Marketplace that puts you first
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Here, your contact details are not shared with third parties unless you request to be contacted by a supplier.
Spotlight
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KYBER IP Core
- supports encapsulation and decapsulation operations
- supports all modes K=2,3,4.
- is compliant with Kyber specification round 3.
- has fully stallable input and output interfaces.
- Key generation feature is going to be implemented in the near future.
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True Random Number Generator (TRNG) IP
- The TRNG IP delivers NIST- and BSI-compliant entropy for secure embedded and SoC designs.
- With robust health testing and digital or analog implementation options, our TRNGs provide the foundation for trusted key generation, encryption, and authentication in mission-critical applications.
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Highly-optimized PQC implementations, capable of running PQC in under 15kb RAM
- PQCryptoLib-Emebedded is a versatile, CAVP-ready cryptography library designed and optimized for embedded devices.
- With its design focused on ultra-small memory footprint, PQCryptoLib-Embedded solutions have been specically designed for embedded systems, microcontrollers and memory-constrained devices. It provides a PQC integration to devices already in the field.
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Audio Sample Rate Converter
- The ASRC core is a compact and high-performance audio sample rate converter.
- It accurately converts digital audio signals between different sample rates while maintaining signal integrity and minimizing distortion.
- Supporting both asynchronous and synchronous conversion modes, the low latency ASRC can be used in real-time streaming applications as well as in high-speed batch processing environments.
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Cryptographic Cores IP
- The Cryptographic Cores IP portfolio delivers secure, high-performance implementations of symmetric, asymmetric, and post-quantum algorithms.
- Designed for low-area, low-latency operation, the silicon-proven cores help SoC designers and embedded teams build trusted, efficient devices for IoT, automotive, medical, and industrial markets.
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DVB-S2X Wideband LDPC/ BCH Encoder
- Compliant with ETSI EN 302 307’
- Compliant with ETSI EN 302 307-2’
- Supports BCH-LDPC all code rates for digital video broadcasting
UCIe Controller IP View All
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UCIe Die-to-Die Chiplet Controller
- High configurability and customizability
- Defines packets to communicate with a link partner using different AXI parameters
- Supports raw streaming modes
- Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
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UCIe PHY & D2D Adapter
- 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
- UCIe v1.1 specification
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2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
- High Bandwidth Density and Data Rates
- Package Configurability
- Energy Efficiency
- Fully Integrated Solution
PCIe 7.0 IP View All
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PCIe 7.0 Controller with AXI
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Separate native TX/RX data path separating posted/Non posted/completion traffic
- Handles up to 4 TLPs per cycle
- Advanced PIPE modes and port bifurcation
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PCIe 7.0 PHY IP
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
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PCIe 7.0 PHY in TSMC (N5, N3P)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
- Spread-spectrum clocking (SSC)
AI IP View All
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RISC-V CPU IP
- RISC-V RVA23 Compliant
- >18 SPECint2006/GHz
- 8-wide decode unit
- Advanced branch predictor
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NPU IP for Embedded ML
- Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
- Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
- Future proof architecture that supports the most advanced ML data types and operators
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Future-proof IP for training and inference with leading performance per watt and per dollar
- RISC-V-based AI IP development for enhanced training and inference.
- Silicon-proven solutions tailored for AI workload optimization.
- Energy-efficient performance with industry-leading Perf/W.
MIPI IP View All
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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
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MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
RISC-V IP View All
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32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32/64 Bit RISC-V core
- 5-stage pipeline
- In-order, Single issue
- Multicore Capable (up to 8 cores)
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Dual-issue Linux-capable RISC-V core
- 64-bit RISC-V core
- RVA22 profile
- Linux capable
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RISC-V high performance CPU
- Aggressive eight-wide deep out-of-order pipeline
- Unique 512KB IL2(I-cache) with DL1/DL2 (512KB) split vs unified 1MB L2