The Pulse
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Rapidus Achieves Significant Milestone at its State-of-the-Art Foundry with Prototyping of Leading-Edge 2nm GAA Transistors
2025-07-20T05:31:00+00:00
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SEMIFIVE Files for Pre-IPO Review on KRX
2025-07-18T11:39:00+00:00
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MIPI: Powering the Future of Connected Devices
2025-07-18T06:12:00+00:00
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Innosilicon Scales LPDDR5X/5/4X/4 and DDR5/4 Combo IPs to 28nm and 22nm, Cementing Its Position as the ‘One Stop’ for Memory Interface Solutions
2025-07-18T04:15:00+00:00
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ESD Protection for an High Voltage Tolerant Driver Circuit in 4nm FinFET Technology
2025-07-17T14:56:00+00:00
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Synopsys Completes Acquisition of Ansys
2025-07-17T13:13:00+00:00
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Zephyr 4.0 Now Available for SCR RISC-V IP
2025-07-17T12:05:00+00:00
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Lattice Semiconductor and Missing Link Electronics Become Partners to Accelerate FPGA Design Projects
2025-07-17T11:35:00+00:00
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TSMC Reports Second Quarter EPS of NT$15.36
2025-07-17T11:23:00+00:00
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Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY
2025-07-17T06:24:00+00:00
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Designing the AI Factories: Unlocking Innovation with Intelligent IP
2025-07-16T16:08:00+00:00
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Smarter SoC Design for Agile Teams and Tight Deadlines
2025-07-16T12:45:00+00:00
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SiPearl Tapes Out Rhea1 Processor, Closes Series A, Preps Series B
2025-07-16T12:39:00+00:00
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How to design secure SoCs, Part V: Data Protection and Encryption
2025-07-16T11:24:00+00:00
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Automotive Reckoning: Industry Leaders Discuss the Race to Redefine Car Development
2025-07-16T11:15:00+00:00
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Applied AI in Analog IC Design Migration
2025-07-16T09:23:00+00:00
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Thalia Design Automation launches AMALIA Platform 25.2
2025-07-16T09:12:00+00:00
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Siemens’ Veloce CS selected by Arm for Neoverse Compute Subsystems verification and validation
2025-07-15T23:24:00+00:00
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InPsytech Tapes Out F2F SoIC Design Compliant with UCIE 2.0 Standard Enabling High-Speed Interconnects for 3D Heterogeneous Integration
2025-07-15T16:18:00+00:00
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ESD Alliance Reports Electronic System Design Industry Posts $5.1 Billion in Revenue in Q1 2025
2025-07-15T14:22:00+00:00
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Lattice Expands Low Power, Small FPGA Portfolio with High I/O Density and Secure Device Options
2025-07-15T13:51:00+00:00
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Encarsia: Evaluating CPU Fuzzers via Automatic Bug Injection
2025-07-15T12:12:00+00:00
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Understanding LTTPR: Enabling High-Speed DisplayPort Interconnects in Complex System Designs
2025-07-15T10:45:00+00:00
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GUC Tapes Out Industry-Leading UCIe Face-Up IP for TSMC SoIC-X
2025-07-15T05:23:00+00:00
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LPDDR6: A New Standard and Memory Choice for AI Data Center Applications
2025-07-15T04:54:00+00:00
The Semiconductor IP Marketplace that puts you first
Semi IP Hub's mission is to provide you with a platform where you can find Silicon IP cores for your next project without being harassed by dozens of sellers.
Here, your contact details are not shared with third parties unless you request to be contacted by a supplier.
Spotlight
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All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX
- Ultra-low jitter, less than 300fs RMS integrated between 12kHz to 20MHz.
- Suitable for many RF applications, including LO, clocks for, ADC, DAC, high-speed PHY
- Small die area (< 0.05 sq mm), using a LC tank oscillator
- Output frequency can be from 1 to 2047 times the input reference, up to 8GHz
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USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
- Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
- x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
- Low active and standby power
- Small area for low silicon cost
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TSMC CLN5FF GUCIe LP Die-to-Die PHY
- IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
- This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the
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Ultra Ethernet Verification IP
- The Ultra Ethernet (UE) Verification IP provides an effective & efficient way to verify the components interfacing with Ethernet interface of an IP or SoC.
- The UE VIP is compliant with IEEE standard 802.3-2018 & UE Specifications V1.0.
- This VIP is light weight with easy plug-and-play interface so that there is no hit on the design cycle time.
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Ethernet Switch VLAN 5x100M
- 5 x 100 Mbit/s Ethernet ports.
- Full wire-speed on all ports and all Ethernet frame sizes.
- Store and forward shared memory architecture.
- Support for jumbo packets up to 4087 bytes.
- Passes maximum overlap mesh test (RFC2899) excluding the CPU port, for all packet sizes up to 1518 bytes.
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SOQPSK-TG Demodulator IP Core
- Shaped Offset Quadrature Phase Shift Keying - Telemetry Group (SOQPSK-TG) is a type of QPSK/OQPSK modulation. SOQPSK-TG provides constant-envelope modulation with continuous phase.
- This minimizes spectral occupancy and improves resistance to interference and nonlinear amplification.
UCIe Controller IP View All
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UCIe Die-to-Die Chiplet Controller
- High configurability and customizability
- Defines packets to communicate with a link partner using different AXI parameters
- Supports raw streaming modes
- Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
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UCIe PHY & D2D Adapter
- 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
- UCIe v1.1 specification
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UCIe Die-to-Die PHY
- High Bandwidth Density and Data Rates
- Package Configurability
- Energy Efficiency
- Fully Integrated Solution
PCIe 7.0 IP View All
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PCIe 7.0 Controller with AXI
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Separate native TX/RX data path separating posted/Non posted/completion traffic
- Handles up to 4 TLPs per cycle
- Advanced PIPE modes and port bifurcation
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PCIe 7.0 PHY IP
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
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PCIe 7.0 PHY in TSMC (N5, N3P)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
- Spread-spectrum clocking (SSC)
AI IP View All
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RISC-V CPU IP
- RISC-V RVA23 Compliant
- >18 SPECint2006/GHz
- 8-wide decode unit
- Advanced branch predictor
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NPU IP for Embedded ML
- Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
- Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
- Future proof architecture that supports the most advanced ML data types and operators
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Future-proof IP for training and inference with leading performance per watt and per dollar
- RISC-V-based AI IP development for enhanced training and inference.
- Silicon-proven solutions tailored for AI workload optimization.
- Energy-efficient performance with industry-leading Perf/W.
MIPI IP View All
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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
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MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
RISC-V IP View All
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32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32/64 Bit RISC-V core
- 5-stage pipeline
- In-order, Single issue
- Multicore Capable (up to 8 cores)
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Dual-issue Linux-capable RISC-V core
- 64-bit RISC-V core
- RVA22 profile
- Linux capable
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High-performance RISC-V CPU
- Fully compliant with the RVA23 RISC-V specification
- Comparable PPA to Arm Neoverse V3 / Cortex-X4
- Standard AMBA CHI.E coherent interface for SoC and chiplet integration
- Co-architected with Veyron E2 for seamless vector, AI acceleration, and big-little style heterogeneous compute configurations