The Pulse
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Blueshift Memory starts £2.77 million development project with AP Memory and Syntronix of Taiwan
2025-02-17T15:34:00+01:00
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Podcast: BrainChip’s IP for Targeting AI Applications at the Edge
2025-02-17T14:17:00+01:00
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Qualitas Semiconductor entered into IP Licensing Agreement with a Leading Korean System Semiconductor Design Company
2025-02-17T14:04:00+01:00
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Chips&Media Patents VVC Video Standard, Poised for Additional Royalty Revenue
2025-02-17T13:32:00+01:00
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ARM signs Meta as first chip product customer, says report
2025-02-17T10:37:00+01:00
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OpenTRNG for Random Numbers on Ever-Shrinking Hardware
2025-02-14T21:37:00+01:00
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Ceva, Inc. Announces Fourth Quarter and Full Year 2024 Financial Results
2025-02-14T16:53:00+01:00
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Easy migration from Arm to RISC-V: an L110 case study
2025-02-14T13:30:00+01:00
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Synopsys Expands the Industry's Highest Performance Hardware-Assisted Verification Portfolio to Propel Next-Generation Semiconductor and Design Innovation
2025-02-14T10:01:00+01:00
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An Open-Source Approach to Developing a RISC-V Chip with XiangShan and Mulan PSL v2
2025-02-13T16:11:00+01:00
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Worldwide Silicon Wafer Shipments and Revenue Start Recovery in Late 2024, SEMI Reports
2025-02-13T16:06:00+01:00
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Paras Defence Invests in Logic Fruit Technologies to Boost Defence Tech Capabilities at AERO India 2025
2025-02-13T13:56:00+01:00
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CoMira Solutions introduces its latest 1.6T Ethernet UMAC IP
2025-02-13T08:34:00+01:00
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Imagination’s Chinese partners now running DeepSeek
2025-02-13T07:56:00+01:00
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Secure-IC to Become Cadence’s Security Entity
2025-02-13T07:01:00+01:00
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Siemens & Alphawave Semi partner for AI silicon IP
2025-02-12T15:32:00+01:00
The Semiconductor IP Marketplace that puts you first
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Spotlight
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KYBER IP Core
- supports encapsulation and decapsulation operations
- supports all modes K=2,3,4.
- is compliant with Kyber specification round 3.
- has fully stallable input and output interfaces.
- Key generation feature is going to be implemented in the near future.
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HBM 3 Verification IP
- Compliant to JEDEC HBM SDRAM Specification versionJESD235A.
- Supports Legacy and Pseudo Channel Mode.
- Supports connection to any HBM Memory Controller IPcommunicating with a JESD235A compliant HBM Memory Model.
- Available in all Stack memory size from 8 Gb to 32 Gb (8Channels/Stack).
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PSI5 IP Core Controller for Peripheral Sensor Interface 5 Communication
- Supports bidirectional communication between ECU-to-sensor
- Asynchronous or synchronous operation
- Manchester decoder digital data transmission
- Data transmission speed 125Kbit/s or 189 Kbit/s
- Support up to 6 time slots between SYNC pulses
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CXL Controller
- CXL 3.0 at 64 GT/s (backward compatible to CXL 2.0 and 1.1), in Type 1/2/3 devices with CXL.io/CXL.cache/CXL.mem
- Compliant with PIPE 6.x (32- / 64-bit) specification
- Supports PCIe 6.0, PCIe 5.0, PCIe 4.0, PCIe 3.1/3.0
- Supports x16, x8, x4, x2, x1 link at Gen5, Gen4, Gen3, Gen2, Gen1 speeds
UCIe Controller IP View All
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UCIe Die-to-Die Chiplet Controller
- High configurability and customizability
- Defines packets to communicate with a link partner using different AXI parameters
- Supports raw streaming modes
- Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
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UCIe PHY & D2D Adapter
- 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
- UCIe v1.1 specification
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2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
- High Bandwidth Density and Data Rates
- Package Configurability
- Energy Efficiency
- Fully Integrated Solution
PCIe 7.0 IP View All
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PCIe 7.0 Controller with AXI
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Separate native TX/RX data path separating posted/Non posted/completion traffic
- Handles up to 4 TLPs per cycle
- Advanced PIPE modes and port bifurcation
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PCIe 7.0 PHY IP
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
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PCIe 7.0 PHY in TSMC (N5, N3P)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
- Spread-spectrum clocking (SSC)
AI IP View All
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RISC-V CPU IP
- RISC-V RVA23 Compliant
- >18 SPECint2006/GHz
- 8-wide decode unit
- Advanced branch predictor
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NPU IP for Embedded AI
- Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
- Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
- Future proof architecture that supports the most advanced ML data types and operators
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Future-proof IP for training and inference with leading performance per watt and per dollar
- RISC-V-based AI IP development for enhanced training and inference.
- Silicon-proven solutions tailored for AI workload optimization.
- Energy-efficient performance with industry-leading Perf/W.
MIPI IP View All
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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
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MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
RISC-V IP View All
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32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32/64 Bit RISC-V core
- 5-stage pipeline
- In-order, Single issue
- Multicore Capable (up to 8 cores)
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Dual-issue Linux-capable RISC-V core
- 64-bit RISC-V core
- RVA22 profile
- Linux capable
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RISC-V high performance CPU
- Aggressive eight-wide deep out-of-order pipeline
- Unique 512KB IL2(I-cache) with DL1/DL2 (512KB) split vs unified 1MB L2