The Pulse
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True Circuits Introduces the Low-jitter Digital Ultra+ PLL at the Design Automation Conference
2025-06-20T08:26:00+02:00
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BrainChip Unveils MetaTF 2.13 on newly launched Developer Hub
2025-06-20T08:02:00+02:00
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Launch of BrainChip Developer Hub Accelerates Event-Based AI Innovation on Akida™ Platform with Release of MetaTF 2.13
2025-06-20T07:54:00+02:00
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Cadence Welcomes VLAB Works
2025-06-19T21:24:00+02:00
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Cadence Launches Cache-Coherent HiFi 5s SMP for Next-Gen Audio Applications
2025-06-19T21:20:00+02:00
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Agnisys Ignites DAC 2025 with IDesignSpec Suite v9, IDS-FPGA Launch, AI² and IDS-Integrate Enhancements.
2025-06-19T17:36:00+02:00
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Enabling ‘Few-Shot Learning’ AI with ReRAM
2025-06-19T14:49:00+02:00
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CAST Launches Multi-Channel DMA IP Core Ideal for Streaming Applications
2025-06-19T10:09:00+02:00
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Maximizing the Usability of Your Chip Development: Design with Flexibility for the Future
2025-06-19T09:23:00+02:00
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ZeroRISC Gets $10 Million Funding, Says Open-Source Silicon Security ‘Inevitable’
2025-06-19T09:11:00+02:00
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Why Hardware Security Is Just as Critical as Software Security in Modern Systems
2025-06-19T07:36:00+02:00
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BT Group Joins the CHERI Alliance to Advance Cybersecurity Innovation
2025-06-18T20:54:00+02:00
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VESA® Approves Teledyne LeCroy DisplayPort™ 2.1 PHY Compliance Test Specification Software
2025-06-18T19:09:00+02:00
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Keysight Enables AMD to Showcase Electrical PCI Express® Compliance up to 64 GT/s
2025-06-18T18:53:00+02:00
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Intel Appoints Sales and Engineering Leaders
2025-06-18T16:18:00+02:00
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Baya Systems Celebrates First Year of Hypergrowth After Emerging from Stealth
2025-06-18T16:11:00+02:00
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Astera Labs and Alchip Announce Strategic Partnership to Advance Silicon Ecosystem for AI Rack-Scale Connectivity
2025-06-18T13:22:00+02:00
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Siemens collaborates with Samsung Foundry on advanced node product certifications and EDA innovation
2025-06-18T13:17:00+02:00
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DCD-SEMI Joins MIPI Alliance and Unveils Latest I3C IP at MIPI Plugfest Warsaw 2025
2025-06-18T12:52:00+02:00
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How Arasan’s SoundWire PHY Can Elevate Your Next Audio SoC
2025-06-18T08:20:00+02:00
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CEA-Leti and Soitec Announce Strategic Partnership to Leverage FD-SOI for Enhanced Security of Integrated Circuits
2025-06-18T08:11:00+02:00
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BOS Joins VESA and UCIe to Advance Global Standards in Display and Chiplet Technology
2025-06-17T15:50:00+02:00
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Marvell Develops Industry’s First 2nm Custom SRAM for Next-Generation AI Infrastructure Silicon
2025-06-17T15:45:00+02:00
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Arteris Accelerates AI-Driven Silicon Innovation with Expanded Multi-Die Solution
2025-06-17T15:28:00+02:00
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From I2C to I3C: Evolution of Two-Wire Communication in Embedded Systems
2025-06-17T14:05:00+02:00
The Semiconductor IP Marketplace that puts you first
Semi IP Hub's mission is to provide you with a platform where you can find Silicon IP cores for your next project without being harassed by dozens of sellers.
Here, your contact details are not shared with third parties unless you request to be contacted by a supplier.
Spotlight
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ARC-V RPX Series Functional Safety Processor IP
- The ARC-V™ RPX-110 series functional safety (FS) processors, which include the RPX-110-FS, RPX-115-FS, RPX-110V-FS, and RPX-115V-FS processors simplify development of high-performance safety-critical applications and accelerate ISO 26262 certification for automotive system-on-chips (SoCs).
- The Automotive Safety Integrity Level (ASIL) D compliant processors feature a pre-verified dual-core lockstep implementation including an integrated safety monitor.
- Additionally, they offer the flexibility to operate in an independent “hybrid” mode for ASIL B or non-automotive applications that demand higher performance from the same design.
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High-performance Linux-capable application core with a 12-stage dual-issue out-of-order pipeline, a VPU, cache coherency, and a hypervisor
- SCR9 is a high-performance, silicon-proven, Linux-capable 64-bit RISC-V processor core for entry-level server-class applications and personal computing devices.
- The SCR9 core supports RISC-V standard "I" Integer, "M" Integer Multiplication and Division, "A" Atomic, "C" 16-bit Compressed, "F" Single-Precision Floating-Point, "D" Double-Precision Floating-Point, "V" Vector Operations, "B" Bit Manipulation, and "K" Scalar Cryptography extensions.
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Multi-Channel Streaming DMA Controller
- The MC-SDMA IP core implements a highly configurable, bandwidth-efficient, and easy-to-use Direct Memory Access (DMA) controller that transfers data between the host system’s memory and multiple peripherals equipped with streaming interfaces.
- The core interfaces with the host memory via a manager AMBA® AXI4 (memory-mapped) port and provides access to its configuration and status registers (CSRs) via a subordinate AXI4-Lite or APB4 interface.
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NVMe 2.2 Verification IP
- Compliant with the NVMe 2.2, 2, 1.4, 1.3, 1.2 specification.
- Compliant with PCI Express Specifications 6.3 (64GT/s), 5.0 v1.0(32GT/s), 4.0 v1.0 (16GT/s), 3.0 (8GT/s), 2.0 (5GT/s) and 1.1 (2.5GT/s).
- Compliant with PIPE Specification 6.2, 5.1, 4.4.1.
- NVMe on top of Low Power, AXI, PCIe Gen6/5/4/3 management
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SLM High-Speed Access & Test IP
- The SLM High-Speed Access and Test (HSAT) IP combined with the TestMAX® ALE software uses standard high speed IO interfaces such as PCIe and USB, to get test, debug and monitoring data in and out of an SoC at Gigabit data rates and avoids the need for large numbers of test and interface pins.
- Test time can be reduced because the link between the test time and GPIO data rate is eliminated. Further, this solution provides a key component for Synopsys Silicon Lifecycle Management solution allowing manufacturing tests to be repeated in-system and in-field as well as providing high speed access to PVT and functional monitor dat
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RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- Built on RISC-V and delivered as soft chiplet IP, the Veyron E2X provides scalable, standards-based AI acceleration that customers can integrate and customize freely.
UCIe Controller IP View All
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UCIe Die-to-Die Chiplet Controller
- High configurability and customizability
- Defines packets to communicate with a link partner using different AXI parameters
- Supports raw streaming modes
- Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
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UCIe PHY & D2D Adapter
- 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
- UCIe v1.1 specification
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UCIe Die-to-Die PHY
- High Bandwidth Density and Data Rates
- Package Configurability
- Energy Efficiency
- Fully Integrated Solution
PCIe 7.0 IP View All
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PCIe 7.0 Controller with AXI
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Separate native TX/RX data path separating posted/Non posted/completion traffic
- Handles up to 4 TLPs per cycle
- Advanced PIPE modes and port bifurcation
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PCIe 7.0 PHY IP
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
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PCIe 7.0 PHY in TSMC (N5, N3P)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
- Spread-spectrum clocking (SSC)
AI IP View All
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RISC-V CPU IP
- RISC-V RVA23 Compliant
- >18 SPECint2006/GHz
- 8-wide decode unit
- Advanced branch predictor
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NPU IP for Embedded ML
- Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
- Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
- Future proof architecture that supports the most advanced ML data types and operators
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Future-proof IP for training and inference with leading performance per watt and per dollar
- RISC-V-based AI IP development for enhanced training and inference.
- Silicon-proven solutions tailored for AI workload optimization.
- Energy-efficient performance with industry-leading Perf/W.
MIPI IP View All
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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
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MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
RISC-V IP View All
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32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32/64 Bit RISC-V core
- 5-stage pipeline
- In-order, Single issue
- Multicore Capable (up to 8 cores)
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Dual-issue Linux-capable RISC-V core
- 64-bit RISC-V core
- RVA22 profile
- Linux capable
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High-performance RISC-V CPU
- Fully compliant with the RVA23 RISC-V specification
- Comparable PPA to Arm Neoverse V3 / Cortex-X4
- Standard AMBA CHI.E coherent interface for SoC and chiplet integration
- Co-architected with Veyron E2 for seamless vector, AI acceleration, and big-little style heterogeneous compute configurations