The Pulse

The Semiconductor IP Marketplace that puts you first

Semi IP Hub's mission is to provide you with a platform where you can find Silicon IP cores for your next project without being harassed by dozens of sellers.

Here, your contact details are not shared with third parties unless you request to be contacted by a supplier.

Spotlight

  • KYBER IP Core
    • supports encapsulation and decapsulation operations
    • supports all modes K=2,3,4.
    • is compliant with Kyber specification round 3.
    • has fully stallable input and output interfaces. 
    • Key generation feature is going to be implemented in the near future.
    Block Diagram -- KYBER IP Core
  • HBM 3 Verification IP
    • Compliant to JEDEC HBM SDRAM Specification versionJESD235A.
    • Supports Legacy and Pseudo Channel Mode.
    • Supports connection to any HBM Memory Controller IPcommunicating with a JESD235A compliant HBM Memory Model.
    • Available in all Stack memory size from 8 Gb to 32 Gb (8Channels/Stack).
    Block Diagram -- HBM 3 Verification IP
  • PSI5 IP Core Controller for Peripheral Sensor Interface 5 Communication
    • Supports bidirectional communication between ECU-to-sensor
    • Asynchronous or synchronous operation
    • Manchester decoder digital data transmission
    • Data transmission speed 125Kbit/s or 189 Kbit/s
    • Support up to 6 time slots between SYNC pulses
  • CXL Controller
    • CXL 3.0 at 64 GT/s (backward compatible to CXL 2.0 and 1.1), in Type 1/2/3 devices with CXL.io/CXL.cache/CXL.mem
    • Compliant with PIPE 6.x (32- / 64-bit) specification
    • Supports PCIe 6.0, PCIe 5.0, PCIe 4.0, PCIe 3.1/3.0
    • Supports x16, x8, x4, x2, x1 link at Gen5, Gen4, Gen3, Gen2, Gen1 speeds
    Block Diagram -- CXL Controller
  • UCIe Die-to-Die Chiplet Controller
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    Block Diagram -- UCIe PHY & D2D Adapter
  • 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
    Block Diagram -- 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
  • PCIe 7.0 Controller with AXI
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
  • PCIe 7.0 PHY in TSMC (N5, N3P)
  • RISC-V CPU IP
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded AI
    Block Diagram -- NPU IP for Embedded AI
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar
×
Semiconductor IP