The Semiconductor IP Marketplace

Spotlight

• UCIe D2D Adapter & PHY Integrated IP

  • The D2D Adapter for UCIe combined with the UCIe PHY from a complete UCIe solution ready to support any protocol layer.
  • The offering consists of two IP parts the D2D adapter from Chip Interfaces and the UCIe PHY from Extoll.
  • Chip Interfaces and Extoll collaborate on UCIe technology to create a complete solution for our customers. 
• Low Dropout (LDO) Regulator

  • Input voltage of 1.8V
  • Output voltage of 1.35V
  • Up to 100mA output current.
  • Stable with Off-chip capacitor 1uF
• 16-Bit xSPI PSRAM PHY

  • Supports for both the xSPI and PSRAM Master host controller IPs.
  • Support 500Mbps per line along with the high speed xSPI modes > 50MHz.
• ASIL B Compliant MIPI CSI-2 CSE2 Security Module

  • Supports MIPI - Camera Service Extensions CSE 2.0 specification
  • Automotive‑ compliant: ISO 26262 (ASIL‑B) & ISO 21434
  • Plug‑and‑play with Synopsys CSI‑2 Host Controllers
  • Data integrity protection and optional encryption (AES-CMAC, AES-GMAC, AES-CTR)
• SHA-256 Secure Hash Algorithm IP Core

  • Supports SHA-256 cryptographic algorithm, an one-way hash function compliant to NIST’s FIPS 180-4 standard.
• 5 GHz 150 fs Jitter PLL - GlobalFoundries 22nm

  • Input Frequency: ~100MHz, ~200MHz
  • Output Frequency: 5 GHz
  • RMS Jitter: <150 fs
  • Supply Voltages: 0.8 V, 1.8V 

UCIe Controller IP View All

• UCIe Die-to-Die Chiplet Controller

  • High configurability and customizability
  • Defines packets to communicate with a link partner using different AXI parameters
  • Supports raw streaming modes
  • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
• UCIe PHY & D2D Adapter

  • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
  • UCIe v1.1 specification
• TSMC CLN5FF GUCIe LP Die-to-Die PHY

  • IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
  • This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the

PCIe 7.0 IP View All

• PCIe 7.0 Controller with AXI

  • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
  • Separate native TX/RX data path separating posted/Non posted/completion traffic
  • Handles up to 4 TLPs per cycle
  • Advanced PIPE modes and port bifurcation
• PCIe 7.0 PHY IP

  • Physical Coding Sublayer (PCS) block with PIPE interface
  • Supports PCIe 7.0, encoding, backchannel initialization
  • Lane margining at the receiver
• PCIe 7.0 PHY in TSMC (N5, N3P)

  • Physical Coding Sublayer (PCS) block with PIPE interface
  • Supports PCIe 7.0, encoding, backchannel initialization
  • Lane margining at the receiver
  • Spread-spectrum clocking (SSC)

AI IP View All

• RISC-V CPU IP

  • RISC-V RVA23 Compliant 
  • >18 SPECint2006/GHz
  • 8-wide decode unit
  • Advanced branch predictor
• NPU IP for Embedded ML

  • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
  • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
  • Future proof architecture that supports the most advanced ML data types and operators
• Future-proof IP for training and inference with leading performance per watt and per dollar

  • RISC-V-based AI IP development for enhanced training and inference.
  • Silicon-proven solutions tailored for AI workload optimization.
  • Energy-efficient performance with industry-leading Perf/W.

MIPI IP View All

• MIPI C-PHY/D-PHY Combo IP

  • The MIPI C/D-PHY combo IP is a high-frequency low-power, low cost, physical layer compliant with the MIPI^® Alliance Standard for C-PHY and D-PHY.
  • The PHY can be configured as a MIPI Master or MIPI Slave, supporting camera interface CSI-2 v1.2 or display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-2 v1.0 applications in the C-PHY mode.
• MIPI M-PHY Type 1 G5 2TX2RX - TSMC N7 1.8V, North/South Poly Orientation

  • Compliant with MIPI M-PHY v5.0 specification
  • Supports MIPI UniPro, JEDEC UFS protocols
  • Supports High-Speed (HS) Gear1,
  • Gear2, Gear3, Gear4 and Gear5 A/B modes
  • Supports M-PHY Type-I
• MIPI D-PHY℠ v2.5 IP Core

  • This Tx/Rx transceiver complies with the MIPI Alliance C-PHY℠ v2.0 and D-PHY℠ v2.5 specifications, with world-class area and power dissipation, and is available for a range of foundry processes.
  • This IP delivers 6 Gbps per lane for a max throughput of 24 Gbps in D-PHY℠ mode, and 6 Gsps per trio for a max throughput of 41.04 Gbps in C-PHY℠ mode.

RISC-V IP View All

• 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.

  • 32/64 Bit RISC-V core
  • 5-stage pipeline
  • In-order, Single issue
  • Multicore Capable (up to 8 cores)
• Dual-issue Linux-capable RISC-V core

  • 64-bit RISC-V core
  • RVA22 profile
  • Linux capable
• High-performance RISC-V CPU

  • Fully compliant with the RVA23 RISC-V specification
  • Comparable PPA to Arm Neoverse V3 / Cortex-X4
  • Standard AMBA CHI.E coherent interface for SoC and chiplet integration
  • Co-architected with Veyron E2 for seamless vector, AI acceleration, and big-little style heterogeneous compute configurations