The Pulse
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How the SiFive HiFive Premier P550 is Accelerating Linux Ecosystem Adoption
2025-05-12T06:40:00+02:00
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Architectures and IP for SoC Clocking
2025-05-11T08:55:00+02:00
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PQSecure Partners with Menta to Demonstrate Leakage-Resistant PQC IPs on eFPGA Fabric
2025-05-11T08:26:00+02:00
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Scaling On-Device GPU Inference for Large Generative Models
2025-05-11T07:53:00+02:00
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Input-Triggered Hardware Trojan Attack on Spiking Neural Networks
2025-05-11T07:29:00+02:00
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Skymizer Launches HyperThought: Build Your Own AI Chip with Skymizer’s LPU IP
2025-05-09T14:44:00+02:00
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SiFive and Kinara Partner to Offer Bare Metal Access to RISC-V Vector Processors
2025-05-09T10:45:00+02:00
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Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
2025-05-09T07:04:00+02:00
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Chip Design Industry Reaches an AI Inflection Point
2025-05-08T16:24:00+02:00
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Cadence Agentic AI Reduces SoC/System Engineering Time by Months
2025-05-08T15:42:00+02:00
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Panmnesia Kicks off $30M Project to Redefine AI Infrastructure with Chiplets, Manycore Architectures, In-Memory Processing, and CXL
2025-05-08T14:07:00+02:00
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SEGGER and Quintauris are working together to develop products and technology for the open-source RISC-V ecosystem
2025-05-08T14:02:00+02:00
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UMC Reports Sales for April 2025
2025-05-08T09:36:00+02:00
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Arm Reports Quarterly Revenue of Over $1 Billion for First Time in Company’s History
2025-05-08T07:05:00+02:00
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VESA Releases Compliance Test Specification Model for DisplayPort Automotive Extensions Standard
2025-05-08T06:37:00+02:00
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Kyocera Licenses Quadric’s Chimera GPNPU AI Processor IP
2025-05-08T05:44:00+02:00
The Semiconductor IP Marketplace that puts you first
Semi IP Hub's mission is to provide you with a platform where you can find Silicon IP cores for your next project without being harassed by dozens of sellers.
Here, your contact details are not shared with third parties unless you request to be contacted by a supplier.
Spotlight
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ORAN IP core
- ORAN IP core is a highly scalable and silicon agnostic implementation of the interoperable O-RAN WG4 defined 7.2x interface for deployment in O-DU and O-RU products, targeting any ASIC, FPGA or ASSP technologies.
- The ORAN over eCPRI implementation builds on long-time experience designing CPRI and Radio-Over-Ethernet solutions for fronthaul and delivers a flexible engine that is prepared for tight integration with software applications.
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E-Series GPU IP
- E-Series GPU IP delivers fast and flexible parallel compute that scales from wearables to the cloud.
- E-Series represents a new era of GPU IP with the introduction of a lot of dense, deeply integrated acceleration for power-efficient AI operations – up to 4x more than Imagination D-Series GPU IP.
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4-port Receiver/Transmitter/Repeater HDCP 2.3 on HDMI 2.0 and/or DisplayPort 2.0/1.4 ESM (generation 3)
- The Multiport/Multiprotocol HDCP 2.2/2.3 Embedded Security Modules (ESMs) are autonomous modules that provide designers with complete and robust transmitter (TX), receiver (RX) and repeater (Rep) implementations of the HDCP 2.3 content protection technology over HDMI 2.1/2.0, DisplayPort 2.0/1.4, and USB 3.x Type-C wired connections.
- These solutions help designers shorten development cycles and fully meet the stringent security requirements of the DCP LLC licensing authority.
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AI IP Core
- The low-power and high-perFormance Al IP developed by DeepMentor integrates the SOC of RISC-V. Customers can quickly integrate a unique combination oF silicon intellectual property into an Al SOC chip.
- System manufacturers do not need to worry about the problems of Al soFtware integration and system development, and can immediately have unique AI products in the market
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All-In-One RISC-V NPU
- Optimized Neural Processing for Next-Generation Machine Learning with High-Efficiency and Scalable AI compute
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On-Die PDN Analyzer for Transistor-Level Visibility and Telemetry
- The Aeonic Insight™ PDN IQ is an in-situ, on-die PDN (Power Delivery Network) analyzer providing transistorlevel PDN telemetry at nanosecond scale.
- The telemetry provided can be applied across the silicon lifecycle to optimize power, performance, and reliability.
- PDN IQ can be used to characterize V-F curves to develop an optimal setpoint to balance power and performance.
UCIe Controller IP View All
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UCIe Die-to-Die Chiplet Controller
- High configurability and customizability
- Defines packets to communicate with a link partner using different AXI parameters
- Supports raw streaming modes
- Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
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UCIe PHY & D2D Adapter
- 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
- UCIe v1.1 specification
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2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
- High Bandwidth Density and Data Rates
- Package Configurability
- Energy Efficiency
- Fully Integrated Solution
PCIe 7.0 IP View All
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PCIe 7.0 Controller with AXI
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Separate native TX/RX data path separating posted/Non posted/completion traffic
- Handles up to 4 TLPs per cycle
- Advanced PIPE modes and port bifurcation
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PCIe 7.0 PHY IP
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
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PCIe 7.0 PHY in TSMC (N5, N3P)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
- Spread-spectrum clocking (SSC)
AI IP View All
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RISC-V CPU IP
- RISC-V RVA23 Compliant
- >18 SPECint2006/GHz
- 8-wide decode unit
- Advanced branch predictor
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NPU IP for Embedded ML
- Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
- Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
- Future proof architecture that supports the most advanced ML data types and operators
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Future-proof IP for training and inference with leading performance per watt and per dollar
- RISC-V-based AI IP development for enhanced training and inference.
- Silicon-proven solutions tailored for AI workload optimization.
- Energy-efficient performance with industry-leading Perf/W.
MIPI IP View All
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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
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MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
RISC-V IP View All
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32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32/64 Bit RISC-V core
- 5-stage pipeline
- In-order, Single issue
- Multicore Capable (up to 8 cores)
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Dual-issue Linux-capable RISC-V core
- 64-bit RISC-V core
- RVA22 profile
- Linux capable
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RISC-V high performance CPU
- Aggressive eight-wide deep out-of-order pipeline
- Unique 512KB IL2(I-cache) with DL1/DL2 (512KB) split vs unified 1MB L2