The Semiconductor IP Marketplace

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Spotlight

  • ARC-V RPX Series Functional Safety Processor IP
    • The ARC-V™ RPX-110 series functional safety (FS) processors, which include the RPX-110-FS, RPX-115-FS, RPX-110V-FS, and RPX-115V-FS processors simplify development of high-performance safety-critical applications and accelerate ISO 26262 certification for automotive system-on-chips (SoCs).
    • The Automotive Safety Integrity Level (ASIL) D compliant processors feature a pre-verified dual-core lockstep implementation including an integrated safety monitor.
    • Additionally, they offer the flexibility to operate in an independent “hybrid” mode for ASIL B or non-automotive applications that demand higher performance from the same design.
    Block Diagram -- ARC-V RPX Series Functional Safety Processor IP
  • High-performance Linux-capable application core with a 12-stage dual-issue out-of-order pipeline, a VPU, cache coherency, and a hypervisor
    • SCR9 is a high-performance, silicon-proven, Linux-capable 64-bit RISC-V processor core for entry-level server-class applications and personal computing devices.
    • The SCR9 core supports RISC-V standard "I" Integer, "M" Integer Multiplication and Division, "A" Atomic, "C" 16-bit Compressed, "F" Single-Precision Floating-Point, "D" Double-Precision Floating-Point, "V" Vector Operations, "B" Bit Manipulation, and "K" Scalar Cryptography extensions.
    Block Diagram -- High-performance Linux-capable application core with a 12-stage dual-issue out-of-order pipeline, a VPU, cache coherency, and a hypervisor
  • Multi-Channel Streaming DMA Controller
    • The MC-SDMA IP core implements a highly configurable, bandwidth-efficient, and easy-to-use Direct Memory Access (DMA) controller that transfers data between the host system’s memory and multiple peripherals equipped with streaming interfaces.
    • The core interfaces with the host memory via a manager AMBA® AXI4 (memory-mapped) port and provides access to its configuration and status registers (CSRs) via a subordinate AXI4-Lite or APB4 interface.
    Block Diagram -- Multi-Channel Streaming DMA Controller
  • NVMe 2.2 Verification IP
    • Compliant with the NVMe 2.2, 2, 1.4, 1.3, 1.2 specification.
    • Compliant with PCI Express Specifications 6.3 (64GT/s), 5.0 v1.0(32GT/s), 4.0 v1.0 (16GT/s), 3.0 (8GT/s), 2.0 (5GT/s) and 1.1 (2.5GT/s).
    • Compliant with PIPE Specification 6.2, 5.1, 4.4.1.
    • NVMe on top of Low Power, AXI, PCIe Gen6/5/4/3 management
    Block Diagram -- NVMe 2.2 Verification IP
  • SLM High-Speed Access & Test IP
    • The SLM High-Speed Access and Test (HSAT) IP combined with the TestMAX® ALE software uses standard high speed IO interfaces such as PCIe and USB, to get test, debug and monitoring data in and out of an SoC at Gigabit data rates and avoids the need for large numbers of test and interface pins.
    • Test time can be reduced because the link between the test time and GPIO data rate is eliminated. Further, this solution provides a key component for Synopsys Silicon Lifecycle Management solution allowing manufacturing tests to be repeated in-system and in-field as well as providing high speed access to PVT and functional monitor dat
    Block Diagram -- SLM High-Speed Access & Test IP
  • RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
    • Built on RISC-V and delivered as soft chiplet IP, the Veyron E2X provides scalable, standards-based AI acceleration that customers can integrate and customize freely.
    Block Diagram -- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP

UCIe Controller IP View All

  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • UCIe Die-to-Die PHY
    • High Bandwidth Density and Data Rates
    • Package Configurability
    • Energy Efficiency
    • Fully Integrated Solution
    Block Diagram -- UCIe Die-to-Die PHY

PCIe 7.0 IP View All

  • PCIe 7.0 Controller with AXI
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Separate native TX/RX data path separating posted/Non posted/completion traffic
    • Handles up to 4 TLPs per cycle
    • Advanced PIPE modes and port bifurcation
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
  • PCIe 7.0 PHY in TSMC (N5, N3P)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SSC)

AI IP View All

  • RISC-V CPU IP
    • RISC-V RVA23 Compliant 
    • >18 SPECint2006/GHz
    • 8-wide decode unit
    • Advanced branch predictor
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
    • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
    • Future proof architecture that supports the most advanced ML data types and operators
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    • RISC-V-based AI IP development for enhanced training and inference.
    • Silicon-proven solutions tailored for AI workload optimization.
    • Energy-efficient performance with industry-leading Perf/W.
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar

MIPI IP View All

RISC-V IP View All

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