The Pulse

The Semiconductor IP Marketplace that puts you first

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Spotlight

  • All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX
    • Ultra-low jitter, less than 300fs RMS integrated between 12kHz to 20MHz.
    • Suitable for many RF applications, including LO, clocks for, ADC, DAC, high-speed PHY
    • Small die area (< 0.05 sq mm), using a LC tank oscillator
    • Output frequency can be from 1 to 2047 times the input reference, up to 8GHz
    Block Diagram -- All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX
  • USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    • Small area for low silicon cost
    Block Diagram -- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
  • TSMC CLN5FF GUCIe LP Die-to-Die PHY
    • IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
    • This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the
    Block Diagram -- TSMC CLN5FF GUCIe LP Die-to-Die PHY
  • Ultra Ethernet Verification IP
    • The Ultra Ethernet (UE) Verification IP provides an effective & efficient way to verify the components interfacing with Ethernet interface of an IP or SoC.
    • The UE VIP is compliant with IEEE standard 802.3-2018 & UE Specifications V1.0.
    • This VIP is light weight with easy plug-and-play interface so that there is no hit on the design cycle time.
    Block Diagram -- Ultra Ethernet Verification IP
  • Ethernet Switch VLAN 5x100M
    • 5 x 100 Mbit/s Ethernet ports.
    •  Full wire-speed on all ports and all Ethernet frame sizes.
    •  Store and forward shared memory architecture.
    •  Support for jumbo packets up to 4087 bytes.
    •  Passes maximum overlap mesh test (RFC2899) excluding the CPU port, for all packet sizes up to 1518 bytes.
    Block Diagram -- Ethernet Switch VLAN 5x100M
  • SOQPSK-TG Demodulator IP Core
    • Shaped Offset Quadrature Phase Shift Keying - Telemetry Group (SOQPSK-TG) is a type of QPSK/OQPSK modulation. SOQPSK-TG provides constant-envelope modulation with continuous phase.
    • This minimizes spectral occupancy and improves resistance to interference and nonlinear amplification.
    Block Diagram -- SOQPSK-TG Demodulator IP Core
  • UCIe Die-to-Die Chiplet Controller
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    Block Diagram -- UCIe PHY & D2D Adapter
  • UCIe Die-to-Die PHY
    Block Diagram -- UCIe Die-to-Die PHY
  • PCIe 7.0 Controller with AXI
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
  • PCIe 7.0 PHY in TSMC (N5, N3P)
  • RISC-V CPU IP
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar
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