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LPDDR IP

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Search (246)
Compare 246 LPDDR IP from 29 vendors (1 - 10)
  • Block Diagram -- LPDDR6 PHY & Controller
  • LPDDR5X/5/4X/4 PHY & Controller
    • The  LPDDR IP includes a LPDDR5X/5/4X/4 Combo PHY and controller.
    • It is fully compliant with the JEDEC standard. Optimized for low-power and high-speed applications, it ensures robust timing and a small silicon area.
    • The PHY IP contains specialized functions to guarantee high-performance I/Os, critical timing, low power and jitter with programmable fine-grain control for any SDRAM interface.
    Block Diagram -- LPDDR5X/5/4X/4 PHY & Controller
  • HBM 4 Verification IP
    • The HBM4 Verification IP provides an effective & efficient way to verify the components interfacing with HBM interface of an ASIC/FPGA or SoC.
    • The HBM4 VIP is fully compliant with Standard HBM Version JESD270-4 specifications from JEDEC.
    • This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design time and the simulation time.
    Block Diagram -- HBM 4 Verification IP
  • LPDDR6 Verification IP
    • The LPDDR6 Verification IP provides an effective & efficient way to verify the LPDDR6 components of an IP or SoC.
    • The VIP is lightweight, featuring easy-to-use plug-and-play components, so there is no impact on the design cycle time.
    Block Diagram -- LPDDR6 Verification IP
  • HBM4E PHY and controller
    • Advanced clocking architecture minimizes clock jitter
    • DFI PHY Independent Mode for initialization and training
    • IEEE 1500 interface, memory BIST feature, and loop-back function
    • Supports lane repair
    Block Diagram -- HBM4E PHY and controller
  • Verification IP for HBM
    • HBM VIP is a comprehensive memory VIP solution portfolio for high bandwidth memory (HBM), targeting a new standard in memory performance, density, power consumption, and cost.
    • HBM VIP is intended for SoC and memory control ler designers who employ external HBM modules and PHY developers to ensure both comprehensive verification and protocol and timing compliance.
    Block Diagram -- Verification IP for HBM
  • TSMC CLN3FFP HBM4 PHY
    • IGAHBMZ03A is a High Bandwidth Memory 4 Physical  Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4.
    • Fabricated in the TSMC 3 nm Advanced process node (N3P), it supports the data rate up to 12 Gbps per data pin in the DDR PHY Interface (DFI)-like 1:4 clock frequency ratio (HBM4 controller clock: WDQS = 1:4).
    Block Diagram -- TSMC CLN3FFP HBM4 PHY
  • HBM4 Memory Controller
    • Supports HBM4 memory devices
    • Supports all standard HBM4 channel densities (up to 32 Gb)
    • Supports up to 10 Gbps/pin
    • Refresh Management (RFM) support
    • Maximize memory bandwidth and minimizes latency via Look Ahead command processing
    • Integrated Reorder functionality
    Block Diagram -- HBM4 Memory Controller
  • High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X
    • The HBM3 IP consists of a PHY and memory controller optimized for Samsung SF4X process to support the HBM3 memory standard (JESD238A) operating at up to 9.6 Gbps/pin.
    • The HBM3 IP is designed for high memory throughput and low latency applications while minimizing area and power consumption.
    Block Diagram -- High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X
  • HBM4/3E Combo PHY & Controller
    • The fourth-generation and third-generation HBM (HBM4/3E) technology is outlined by the JESD238A standard (for HBM3E) and an upcoming specification (for HBM4)
    • These technologies feature 256-bit memory access per channel, with a 1024-bit input/output interface for HBM3E and up to a 2048-bit interface for HBM4
    Block Diagram -- HBM4/3E Combo PHY & Controller
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