LPDDR IP

Compare 179 LPDDR IP from 23 vendors (1 - 10)

LPDDR5X/5/4X/4 PHY & Controller
- The DDR IP Mixed-Signal LPDDR5X/5/4X/4 Combo PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices
- It is optimized for low-power and high-speed applications with robust timing and small silicon area
- It supports all JEDEC LPDDR5X/5/4X/4 SDRAM components in the market
- The PHY components contain DDR-specialized functional and utility high-performance I/Os, critical timing synchronization modules (TSM), and low power/jitter DLLs with programmable fine-grain control for any SDRAM interface
LPDDR5X/5/4X/4 combo PHY at 12nm
- Compliant with JEDEC JESD209-5C for LPDDR5x/5/4x/4 with PHY standards
- Delivering up to 8533Mbps
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
- Multiple frequency states
LPDDR5X/5/4X/4 PHY for 16nm
- Compliant with JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
- DFI 5.0 Interface Compliant
- Supports up to 4 ranks
- Multiple frequency states
LPDDR5/4x/4 combo PHY on 14nm, 12nm
- Compliant with JEDEC standards for LPDDR5/4x/4 with PHY standards
- DFI 5.0 Interface Compliant
- Supports 1,2, or 4 ranks
- Multiple frequency states
LPDDR5/4x/4 PHY IP for Samsung 14LPU
- Compliant with JEDEC standards for LPDDR5/4x/4 with PHY standards
- DFI 5.0 Interface Compliant
- Supports 1,2, or 4 ranks
- Multiple frequency states
LPDDR4x/4 PHY IP for 22nm
- Compliant for JEDEC standards for LPDDR4x/4 with PHY standards
- DFI Interface Compliant
- Supports 1,2, or 4 ranks
- Multiple frequency states
Memory Controller
- JEDEC GDDR6 standard JESD250B
- Fast frequency switching
- Flexible Configuration
Universal Multi-port Memory Controller for RLDRAM2/3, DDR4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2
- The UMMC Controller is a highly flexible and configurable design. It is targeted for high bandwidth access and low power consumption such as next generation mobile, DDR/LPDDR networking and consumer applications.
- The controller architecture is carefully tailored to achieve reliable high-frequency operation with dynamic power management and rapid system debug capabilities.
LPDDR5T / LPDDR5X / LPDDR5 Controller
- Support for all LPDDR5T/5X/5 devices
- Bank management logic monitors status of each bank
- Queue-based user interface with reordering scheduler
- Look-ahead activate, precharge, and auto-precharge logic
- Parity protection for all stored control registers
- PHY interface based on DFI 5.1 standard
LPDDR4X / LPDDR4 Controller
- Maximizes bus efficiency via look-ahead command processing, bank management, and auto-precharge
- Latency minimized via parameterized pipelining
- Achieves high clock rates with minimal routing constraints
- Supports full-rate, half-rate and quarter-rate clock operation
- Multi-mode controller support