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Cryptography IP

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Search (329)
Compare 329 Cryptography IP from 57 vendors (1 - 10)
  • ASCON Authenticated Encryption & Hashing Engine
    • The ASCON-F IP core is a compact, high-throughput hardware engine implementing the lightweight authenticated encryption with associated data (AEAD) and hashing algorithms described in the Ascon v1.2 specification. 
    • A single instance of the ASCON-F IP core can encrypt or decrypt data using the Ascon-128 and Ascon-128a functions or perform Cryptographic hashing Hash per the Ascon-Hash and Ascon-Hasha functions.
    Block Diagram -- ASCON Authenticated Encryption & Hashing Engine
  • SM4 Cipher Engine
    • The SM4 IP core implements a custom hardware accelerator for the SM4 symmetric block cipher, specified in Chinese national standard GB/T 32907-2016, and ISO/IEC 18033-3:2010/Amd 1:2021.
    • Designed for easy integration, the core, internally expanding the 128-bit key, is capable of both encryption and decryption and features a simple handshake input and output data interface.
    Block Diagram -- SM4 Cipher Engine
  • SNOW-V Stream Cipher Engine
    • The SNOW-V IP core implements the SNOW-V stream cipher mechanism, aiming to meet the security demands of modern high-speed communication systems.
    • It conforms to the official SNOW-V mechanism, published in 2019 by the IACR Transactions on Symmetric Cryptology, as an extensive revision of SNOW 3G stream cipher.
    Block Diagram -- SNOW-V Stream Cipher Engine
  • ML-DSA Digital Signature Engine
    • The KiviPQC™-DSA is a hardware accelerator for post-quantum cryptographic operations.
    • It implements the Module Lattice-based Digital Signature Algorithm (ML-DSA), standardized by NIST in FIPS 204.
    • This mechanism realizes the appropriate procedures for securely generating a private/public key pair, digitally signing a message or a data block, and performing digital signature verification. 
    Block Diagram -- ML-DSA Digital Signature Engine
  • ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
    • The KiviPQC™-Box is a hardware accelerator for post-quantum cryptographic operations.
    • It implements both the Module Lattice-based Key Encapsulation Mechanism (ML-KEM) and the Module Lattice-based Digital Signature Algorithm (ML-DSA), standardized by NIST in FIPS 203 and FIPS 204, respectively.
    Block Diagram -- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
  • ML-KEM Key Encapsulation IP Core
    • The KiviPQC™-KEM is a hardware accelerator for post-quantum cryptographic operations.
    • It implements the Module Lattice-based Key Encapsulation Mechanism (ML-KEM), standardized by NIST in FIPS 203.
    • This mechanism realizes the appropriate procedures for securely exchanging a shared secret key between two parties that communicate over a public channel using a defined set of rules and parameters. 
    Block Diagram -- ML-KEM Key Encapsulation IP Core
  • P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
    • Small size: From 70K ASIC gates (at throughput of 18.2 bits per clock)
    • 500 MHz frequency in 90 nm process
    • Easily parallelizable to achieve higher throughputs
    • Completely self-contained: does not require external memory. Includes encryption, decryption, key expansion and data interface
    Block Diagram -- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
  • AES-SX Secure Core - High-Throughput AES Core with Advanced SCA/FI Protection for Performance-Critical Systems
    • The High-Performance AES IP core is a fast, silicon-proven cryptographic engine designed for systems with demanding encryption workloads.
    • Built on a 20 S-box parallel architecture, it delivers exceptional AES-128/256 encryption and decryption throughput while supporting standard modes including ECB, CBC, and CTR (excluding GCM, XTS, and CBC-MAC).
    Block Diagram -- AES-SX Secure Core - High-Throughput AES Core with Advanced SCA/FI Protection for Performance-Critical Systems
  • Crypto Coprocessor with integrated Post-Quantum Cryptography IPs
    • The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.
    • Symmetric operations are offloaded very efficiently as it has a built-in scatter/gather DMA. The coprocessors can be used to accelerate/offload IPsec, VPN, TLS/SSL, disk encryption, or any custom application requiring cryptography algorithms.
    Block Diagram -- Crypto Coprocessor with integrated Post-Quantum Cryptography IPs
  • Deterministic Random Bit Generator (DRBG)
    • The Deterministic Random Bit Generator is an essential silicon-proven digital IP core for all FPGA, ASIC and SoC designs that targets cryptographically secured applications.
    • It is a deterministic algorithm compliant with the NIST-800-90A Rev1.
    • The IP Core successfully passed NIST-800-90A Rev1 test suites and it is compliant with the FIPS-140-2 validation.
    Block Diagram -- Deterministic Random Bit Generator (DRBG)
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