Cryptography IP
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Cryptography IP
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AES-SX Secure Core - High-Throughput AES Core with Advanced SCA/FI Protection for Performance-Critical Systems
- The High-Performance AES IP core is a fast, silicon-proven cryptographic engine designed for systems with demanding encryption workloads.
- Built on a 20 S-box parallel architecture, it delivers exceptional AES-128/256 encryption and decryption throughput while supporting standard modes including ECB, CBC, and CTR (excluding GCM, XTS, and CBC-MAC).
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Crypto Coprocessor with integrated Post-Quantum Cryptography IPs
- The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.
- Symmetric operations are offloaded very efficiently as it has a built-in scatter/gather DMA. The coprocessors can be used to accelerate/offload IPsec, VPN, TLS/SSL, disk encryption, or any custom application requiring cryptography algorithms.
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Deterministic Random Bit Generator (DRBG)
- The Deterministic Random Bit Generator is an essential silicon-proven digital IP core for all FPGA, ASIC and SoC designs that targets cryptographically secured applications.
- It is a deterministic algorithm compliant with the NIST-800-90A Rev1.
- The IP Core successfully passed NIST-800-90A Rev1 test suites and it is compliant with the FIPS-140-2 validation.
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AES-XTS Multi-Booster
- The AES-XTS Multi-Booster crypto engine includes a generic & scalable implementation of the AES algorithm making the solution suitable for a wide range of low-cost & high-end applications (including key, tweak, input and output registers and Galois field multiplier).
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AES Mutli-Purpose crypto engine
- The AES Multi-Purpose crypto engine includes a generic and scalable implementation of the AES algorithm and a configurable wrapper making the solution suitable for a wide range of low-cost & high-end applications.
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True Random Number Generator (TRNG)
- Fully Digital and based on standard cells
- Compliant with: AIS-31 (PTG.1 to PTG.3), NIST FIPS 140-3, NIST SP 800-90, GM/T 0005-2015
- Robust against process, temperature and voltage variations
- Post-silicon fine tuning to ensure high-level functional safety
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SHA-3 Crypto Engine
- The SHA-3 crypto engine has integrated flexibility and scalability to allow for high throughput and a configurable number of hashing rounds per clock cycle to optimize the silicon resource/performance ratio.
- Fixed-length or extendable-output (XOF) functions can simply be chosen per individual message through configuration settings.
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Hash Crypto Engine
- The Hash Crypto Engine is flexible and optimized hash IP core compliant with FIPS 180-3 (HASH functions), FIPS 198 (HMAC function) and OSCCA (SM3).
- With a flexible wrapper supporting a wide selection of programmable hashing modes (SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SM3 and MD5) with HMAC and several options of data interface, the Hash Crypto Engine is an easy-to-use solution with predictable resources and performances on ASIC and FPGA.
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3DES Crypto Engine
- The DES/3DES crypto engine offers a hardware implementation of the Data Encryption Standard (DES) according to Federal Information Processing Standards Publication (FIPS 46-3) of the National Institute of Standards and Technology (NIST).
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KASUMI Crypto Engine
- The KASUMI IP core is 3GPP confidentiality and integrity algorithms (UEA1/UIA1) stream cipher for telecommunication applications, requiring high performance with reduced silicon resources.
- It is optimized for maximum throughput and minimum latency.
