Clocking IP

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Compare 2,947 Clocking IP from 76 vendors (1 - 10)
  • Oscillator on Samsung 28nm LNM28FDS
    • OSC2802X is a 1V oscillator with output frequency of 240kHz.
    • It consists of an oscillator (OSC) and a current reference.
    Block Diagram -- Oscillator on Samsung 28nm LNM28FDS
  • Integer PLL on Samsung 8nm LN08LPP
    • PLLF0816X is a 1.8V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
    • It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre divider, a 10-bit main-divider, a 3-bit scaler, and an automatic frequency control (AFC).
    Block Diagram -- Integer PLL on Samsung 8nm LN08LPP
  • Integer PLL on Samsung 28nm LN28FDS
    • PLL2851X is a 1.8V/1.0V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
    • It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre divider, a 10-bit main-divider, a 3-bit scaler, a lock detector and an automatic frequency control (AFC). The maximum output frequency of PLL is 2.5GHz.
    Block Diagram -- Integer PLL on Samsung 28nm LN28FDS
  • Frac-N PLL on Samsung 8nm LN08LPP
    • PLLF0842X is a 1.8V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
    • It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre divider, a 10-bit main-divider, a 3-bit scaler, a delta-sigma modulator (DSM) and an automatic frequency control (AFC).
    Block Diagram -- Frac-N PLL on Samsung 8nm LN08LPP
  • Frac-N PLL on Samsung 4nm LN04LPP
    • PLLF0434X is a 1.2V/0.75V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
    • It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre-divider, a 10-bit main-divider, a 3-bit scaler, a delta-sigma modulator (DSM) and an automatic frequency control (AFC).
    Block Diagram -- Frac-N PLL on Samsung 4nm LN04LPP
  • Frac-N PLL on Samsung 28nm LN28FDS
    • PLL2860X is a 1.8V/1.0V dual supply-voltage phase locked loop (PLL) with a wide-output-frequency-range for frequency synthesis.
    • It consists of a phase frequency detector (PFD), a charge pump, a voltage-controlled oscillator (VCO), a 6-bit pre divider, a 10-bit main-divider, a 3-bit scaler, a delta-sigma modulator (DSM) and an automatic frequency control (AFC).
    Block Diagram -- Frac-N PLL on Samsung 28nm LN28FDS
  • Integer-N-PLL-based HF Frequency Synthesizer and Clock Generator with integrated Loop Filter and VCO
    • This integer-N PLL synthesizes 3.3V-square-wave FVCO frequencies within the HF range from 2.424MHz up to 9.697MHz, by steps of 18.9393kHz, and provides one fourth of fVCO on two other outputs, FDEM and FDRV, which feature quadrature phase difference or no phase shift depending on the control bit PH_SEL.
    • The PLL-locked state within ±0.08% of fVCO is signaled by a logic high level on the LOCK output.
    Block Diagram -- Integer-N-PLL-based HF Frequency Synthesizer and Clock Generator with integrated Loop Filter and VCO
  • Multi-rate Audio 24-Bit DAC/PLL Core
    • Operates from single 27/54MHz clock.
    • Ideal for MPEG, AC-3, DVD systems
    • Internally generates audio sample clocks
    • Multi-sample rates: 32, 44.1, 48 KHz
    Block Diagram -- Multi-rate Audio 24-Bit DAC/PLL Core
  • High Speed 16GHz PLL
    • Type II ,3rd order low jitter PLL
    • Auto calibration for process and temperature (USP)
    • Programmable frequency using CSR registers
    • 8/10/16GHz quadrature clocks
    • Operating temperature -40 to 125
    Block Diagram -- High Speed 16GHz PLL
  • 40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
    • Rail-to-Rail IQ ADC Input Capability
    • 65dB IQ ADC SNR
    • Programmable Full-Scale IQ DAC Output Current
    • 65dB IQ DAC SNR
    Block Diagram -- 40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
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