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Clocking IP

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Compare 2,954 Clocking IP from 75 vendors (1 - 10)
  • 1.7GHz Multiplying PLL on TSMC 28nm
    • Including Loop-filter
    • VCO operating range : 850MHz - 1700 MHz
    • Output frequency range : 850MHz -1700 MHz
    • Input frequency range : 9.6MHz - 216MHz
    Block Diagram -- 1.7GHz Multiplying PLL on TSMC 28nm
  • 5GHz Multiplying PLL on TSMC 28nm
    • Including Loop-filter
    • VCO operating range : 2500MHz - 5000 MHz
    • Output frequency range : 1250MHz - 2500 MHz
    • Input frequency range : 12MHz - 320 MHz
    Block Diagram -- 5GHz Multiplying PLL on TSMC 28nm
  • 1.8GHz SSCG PLL on TSMC 28nm HPC+
    • Including Loop-filter
    • VCO operating range : 900MHz - 1800 MHz
    • Output frequency range : 900MHz-1800 MHz
    • Input frequency range : 12MHz - 192MHz
    Block Diagram -- 1.8GHz SSCG PLL on TSMC 28nm HPC+
  • 3.2GHz SSCG PLL on TSMC 12nm
    • Including Loop filter
    • VCO operating range : 1600MHz- 3200MHz
    • Output frequency range: 400MHz- 3200MHz
    • Input frequency range : 10MHz- 200MHz
    Block Diagram -- 3.2GHz SSCG PLL on TSMC 12nm
  • 4.3GHz SSCG PLL on TSMC 7nm
    • Including Loop filter
    • VCO operating range : 2000MHz-4300MHz
    • Output frequency range: 500MHz-4300MHz
    • Input frequency range : 10MHz- 200MHz
    Block Diagram -- 4.3GHz SSCG PLL on TSMC 7nm
  • Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
    • TSMC IP9000 Alliance member enabling automotive IP support in TSMC automotive processes
    • Automotive Documentation including Safety Manual, FMEDA and DFMEA
    • Design reliability report containing EM/IR and Aging analysis
    Block Diagram -- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
  • General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
    • This Integer-N Hybrid (Digitally Aided Analog) PLL generates clock signals within broad frequency range.
    • Division coefficients of the embedded input and feedback dividers can be set to any integer between 1 and 64 or may be bypassed to save power.
    • Higher order dividers and/or pre-scalers are optional.
    Block Diagram -- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
  • All Digital Fractional-N PLL for Performance Computing in UMC 40LP
    • Fractional multiplication with frequency up to 4GHz
    • Low jitter (< 10ps RMS)
    • Small size  (< 0.01 sq mm)
    • Low Power (< 5mW)
    Block Diagram -- All Digital Fractional-N PLL for Performance Computing in UMC 40LP
  • 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
    • 055SMIC_PLL_01 forms clock output signal with frequency from 50 to 800MHz.
    • It consists of the ring VCO with frequency from 400 to 800MHz, a programmable feedback divider, a low noise digital phase noise detector (PFD), a precision charge pump (CP) with internal loop filter, lock detector (LD) and programmable clock divider to obtain a required output frequency.
    • LO output signal is CMOS compatible.
    Block Diagram -- 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
  • Ultra low-power crystal-based 32 kHz oscillator in TSMC 12FFC+
    • OSC-XT-32k-T12FFC.01_TSMC_12_FFC+ is an ultra-low power crystal-based oscillator in TSMC 12FFC+ for accurate 32 kHz clock generation in the SoC Always-On domain (eg. implementation of RTC features).
    • An embedded auxiliary loop controls the voltage amplitude at the crystal terminals for maximizing the power efficiency for multiple crystals.
    Block Diagram -- Ultra low-power crystal-based 32 kHz oscillator in TSMC 12FFC+
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