Clocking IP
All offers in
Clocking IP
Filter
Compare
2,306
Clocking IP
from 57 vendors
(1
-
10)
-
Ultra-low power 32 kHz RC oscillator designed in GlobalFoundries 22FDX
- Ultra-low power for best-in-class power consumption of the always-on domain during sleep / deep sleep modes
- Fast wake-up
- Active, shutdown and stand-by mode
-
CC-100IP-PI Power Integrity Enhancement IP
- Occupies the same on chip area as standard DCAPs with at least a 600X effective capacitance increase
- Up to a 36% Dynamic Power and RF Emissions Reduction
- On-Chip Cybersecurity Enhancement
- 25% Reduction in Capacitor ESL
-
High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
- Fractional-N digital PLL architecture, using an LC-tank oscillator
-
High Performance Fractional-N RF Frequency Synthesizer PLL in UMC 40LP
- Fractional-N digital PLL architecture, using an LC-tank oscillator
- Ultra-low jitter and ultra-low phase noise
-
40nm 1.1V 6.0GHz-9.4GHz Fractional-N RF PLL
- TSMC 40nm CMOS
- 6.0GHz-to-9.7GHz Buffered VCO PLL Output Coverage
- Scalable Power Consumption
-
40nm 1.1V 2GHz-4.7GHz Fractional-N RF Quadrature PLL
- 2.0GHz-to-4.7GHz PLL Output Coverage
- Scalable Power Consumption
-
40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
- Rail-to-Rail IQ ADC Input Capability
- 65dB IQ ADC SNR
- Programmable Full-Scale IQ DAC Output Current
- 65dB IQ DAC SNR
-
40nm 1.1V 16MHz-2GHz Fractional-N Clock-PLL
- 16MHz-to-2GHz PLL Output Coverage
- Scalable Power Consumption
- Three independent programmable PLL outputs
- Internal Calibration Engine and Convergence Algorithm
-
Low Voltage, Low Power Fractional-N PLLs
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
-
Fractional-N PLL for Performance Computing in GlobalFoundries 12LPP/14LPP
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.004 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
