Processor IP
Welcome to the ultimate Processor IP hub!
Our vast directory of Processor IP cores include AI Processor IP, GPU IP, NPU IP, DSP IP, Arm Processor, RISC-V Processor and much more.
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Ultra-low power consumption out-of-order commercial-grade 64-bit RISC-V CPU IP
- Dubhe-70 is a 9+ stage, 3-issue, out-of-order CPU IP that supports the rich RISC-V instruction set, RV64GCBH_Zicond_Zicbom_Zicboz_Zicbop.
- With a score of 7.2 SPECInt2006/GHz, Dubhe-70 targets applications that require highly energy-efficient computation, including mobile, desktop, AI, and automotive.
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64-bit application processor for energy-efficient computation
- Dubhe-80 processor features a 9+ stage, 3-issue, out-of-order pipeline, fully compliant with a rich set of RISC-V extensions of RV64GCBH_Zicond_Zicbom_Zicboz_Zicbop.
- With a score of 8.5 SPECInt2006/GHz, Dubhe-80 is designed for mobile, desktop, AI, and automotive applications that require highly energy-efficient computation.
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CPU IP Following the RVA23 Profile, supporting RVV1.0 and all extensions of Vector Crypto
- Dubhe-83 CPU IP features a 10+ stage pipeline, 3-issue, and out-of-order pipeline, follows the RVA23 Profile, supports RV64GCBVH, supports RVV1.0 and supports all extensions of Vector Crypto.
- With a score of 8.5 SPECInt2006/GHz, Dubhe-83 targets applications that require highly energy-efficient computation, including mobile, desktop, AI, and automotive.
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High Performance 64-bit RISC-V Processor
- Dubhe-90 is a high-performance commercial RISC-V CPU Core IP that is deliverable.
- It adopts an 11+ stage and 5-issue pipeline, superscalar, and deep out-of-order execution, and supports standard RISC-V RV64GCBH extensions.
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AI/ML Accelerator
- General purpose RISC-V core (RV32IMC)
- Standard communication peripherals: UART, I2C, SPI (x2), Octo-SPI, DCMI, I2S
- JTAG debugging interface
- Up to 4 MB of on-chip SRAM + 0.5MB of MRAM
- Multi neural network execution
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GPNPU Processor IP - 32 to 864TOPs
- 32 to 864TOPs
- (Dual, Quad, Octo Core) Up to 256K MACs
- Hybrid Von Neuman + 2D SIMD matrix architecture
- 64b Instruction word, single instruction issue per clock
- 7-stage, in-order pipeline
- Scalar / vector / matrix instructions modelessly intermixed with granular predication
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GPNPU Processor IP - 16 to 108 TOPs
- 16 to 108 TOPs
- 8K / 16K / 32K MACs plus 1024 ALUs
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GPNPU Processor IP - 1 to 7 TOPs
- 1 to 7TOPs
- 512/ 1K/ 2K/ 8K MACs plus 64 ALUs
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GPNPU Processor IP - 4 to 28 TOPs
- 4 to 28 TOPs
- 2K/ 4K/ 8K MACs plus 256 ALUs
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ARC Functional Safety Software
- The functional safety (FuSa) software components in conjunction with Synopsys’ ASIL certified MetaWare Development Tools for Safety and industry leading ARC® FS processors provide comprehensive ASIL compliant solutions which dramatically reduce customers’ risk and SoC certification effort.
