Processor IP

Compare 664 Processor IP from 112 vendors (1 - 10)

RISC-V Debug & Trace IP
- 10xEngineers Debug & N-Trace IP delivers a unified Debug + Trace solution that provides full-system visibility with low overhead and multi-hart awareness.
- Standards-compliant debug, real-time trace, and flexible triggering significantly reduce bring-up time and simplify system integration.
RISC-V IOPMP IP
- The I/O Physical Memory Protection (IOPMP) unit is a hardware-based access control mechanism designed to safeguard memory regions in RISC-V SoCs.
- It ensures only authorized devices and masters can access sensitive memory areas, enabling secure and reliable system operation.
Embedded AI accelerator IP
- The GenAI IP is the smallest version of our NPU, tailored to small devices such as FPGAs and Adaptive SoCs, where the maximum Frequency is limited (<=250 MHz) and Memory Bandwidth is lower (<=100 GB/s).
NPU IP for AI Vision and AI Voice
- 128-bit vector processing unit (shader + ext)
- OpenCL 3.0 shader instruction set
- Enhanced vision instruction set (EVIS)
- INT 8/16/32b, Float 16/32b
NPU IP for Wearable and IoT Market
- ML inference engine for deeply embedded system
  NN Engine
  Supports popular ML frameworks
  Support wide range of NN algorithms and flexible in layer ordering
NPU IP for Data Center and Automotive
- 128-bit vector processing unit (shader + ext)
- OpenCL 1.2 shader instruction set
- Enhanced vision instruction set (EVIS)
- INT 8/16/32b, Float 16/32b in PPU
- Convolution layers
Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex. Designed for a range of applications requiring maximum single thread performance in Linux-capable devices. Improved performance compared with Gen#1.
64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- 64-bit RISC-V core with in-order single issue pipeline based complex.
- Tiny Linux-capable processor optimized for low power and small area.
- Ideally fits IoT applications requiring Linux.
LLM AI IP Core
- For sophisticated workloads, DeepTransformCore is optimized for language and vision applications.
- Supporting both encoder and decoder transformer architectures with flexible DRAM configurations and FPGA compatibility, DeepTransformCore eliminates complex software integration burdens, empowering customers to rapidly develop custom AI SoC (System-on-chip) designs with unprecedented efficiency.
CNN AI IP Core
- DeepMentor has developed an AI IP that combines low-power and high-performance features with the RISC-V SOC.
- This integration allows customers to quickly create unique AI SOC without worrying about software integration or system development issues.
- DeepLogCore supports both RISC-V and ARM systems, enabling faster and more flexible development.

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