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Processor IP

Welcome to the ultimate Processor IP hub!

Our vast directory of Processor IP cores include AI Processor IP, GPU IP, NPU IP, DSP IP, Arm Processor, RISC-V Processor and much more.

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Search (666)
Compare 666 Processor IP from 113 vendors (1 - 10)
  • NPU IP for AI Vision and AI Voice
    • 128-bit vector processing unit (shader + ext)
    • OpenCL 3.0 shader instruction set
    • Enhanced vision instruction set (EVIS)
    • INT 8/16/32b, Float 16/32b
    Block Diagram -- NPU IP for AI Vision and AI Voice
  • NPU IP for Wearable and IoT Market
    • ML inference engine for deeply embedded system
      NN Engine
      Supports popular ML frameworks
      Support wide range of NN algorithms and flexible in layer ordering
    Block Diagram -- NPU IP for Wearable and IoT Market
  • NPU IP for Data Center and Automotive
    • 128-bit vector processing unit (shader + ext)
    • OpenCL 1.2 shader instruction set
    • Enhanced vision instruction set (EVIS)
    • INT 8/16/32b, Float 16/32b in PPU
    • Convolution layers
    Block Diagram -- NPU IP for Data Center and Automotive
  • Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
    • Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex. Designed for a range of applications requiring maximum single thread performance in Linux-capable devices. Improved performance compared with Gen#1.
    Block Diagram -- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
  • 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
    • 64-bit RISC-V core with in-order single issue pipeline based complex.
    • Tiny Linux-capable processor optimized for low power and small area.
    • Ideally fits IoT applications requiring Linux.
    Block Diagram -- 64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
  • LLM AI IP Core
    • For sophisticated workloads, DeepTransformCore is optimized for language and vision applications.
    • Supporting both encoder and decoder transformer architectures with flexible DRAM configurations and FPGA compatibility, DeepTransformCore eliminates complex software integration burdens, empowering customers to rapidly develop custom AI SoC (System-on-chip) designs with unprecedented efficiency.
    Block Diagram -- LLM AI IP Core
  • CNN AI IP Core
    • DeepMentor has developed an AI IP that combines low-power and high-performance features with the RISC-V SOC.
    • This integration allows customers to quickly create unique AI SOC without worrying about software integration or system development issues.
    • DeepLogCore supports both RISC-V and ARM systems, enabling faster and more flexible development.
    Block Diagram -- CNN AI IP Core
  • Vector-Capable Embedded RISC-V Processor
    • The EMSA5-GP is a highly-featured 32-bit RISC-V embedded processor IP core optimized for processing-demanding applications.
    • It is equipped with floating-point and vector-processing units, cache memories, and is suitable for concurrent execution in a multi-processor environment.
    Block Diagram -- Vector-Capable Embedded RISC-V Processor
  • Compact Embedded RISC-V Processor
    • The BA5x-CM is a feature-rich 32-bit deeply embedded processor.
    • Equipped with a floating-point unit and an instruction cache memory and supporting concurrent execution in a multiprocessor environment, it is well-suited to a wide range of edge IoT and similar applications.
    Block Diagram -- Compact Embedded RISC-V Processor
  • Tiny, Ultra-Low-Power Embedded RISC-V Processor
    • The BA5x-TN is a compact, ultra-low power, 32-bit, deeply embedded processor IP core.
    • With a two-stage execution pipeline, the processor implements the Embedded variant of the base RV32 ISA (RV32E).
    • It uses just 16 general-purpose compressed instructions and omits other resource-demanding extensions.
    Block Diagram -- Tiny, Ultra-Low-Power Embedded RISC-V Processor
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