Processor IP

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Our vast directory of Processor IP cores include AI Processor IP, GPU IP, NPU IP, DSP IP, Arm Processor, RISC-V Processor and much more.

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Compare 795 Processor IP from 123 vendors (1 - 10)
  • Multi-core capable 64-bit RISC-V CPU with vector extensions
    • The SiFive® Intelligence™ X180 core IP products are designed to meet the increasing requirements of embedded IoT and AI at the far edge.
    • With this 64-bit version, X100 series IP delivers higher performance and better integration with larger memory systems.
    Block Diagram -- Multi-core capable 64-bit RISC-V CPU  with vector extensions
  • Multi-core capable 32-bit RISC-V CPU with vector extensions
    • The SiFive® Intelligence™ X160 core IP products are designed to meet the increasing requirements of embedded IoT and AI at the far edge.
    • With this 32-bit version, X100 series IP can be optimized for power efficiency and severely area-constrained applications.
    Block Diagram -- Multi-core capable 32-bit RISC-V CPU  with vector extensions
  • Multi-core capable RISC-V processor with vector extensions
    • The SiFive® Intelligence™ X280 Gen 2 is an 8-stage dual issue, in-order, superscalar design with wide vector processing (512 bit VLEN/256-bit DLEN).
    • It supports RISC-V Vectors v1.0 (RVV 1.0) and SiFive Intelligence Extensions to accelerate critical AI/ML operations.
    Block Diagram -- Multi-core capable RISC-V processor with vector extensions
  • Multi-core capable processor
    • The SiFive® Intelligence™ X288 is a multi-core capable processor extensively optimized to meet the harsh environmental and stringent reliability requirements of aerospace and defense applications.
    • The X288 features the powerful combination of a RISC-V 64-bit 8-stage dual-issue in-order scalar pipeline and a 512-bit vector length pipeline.
    Block Diagram -- Multi-core capable processor
  • 8-stage dual issue, in-order, superscalar processor with dual vector processing units (1024-bit VLEN/512-bit DLEN)
    • New RVA23 support 
    • New RVV1.0 512-bit vector engine 
    • New SSCI interface added alongside VCIX 
    • New instructions and extensions 
    • New improved memory subsystem 
    Block Diagram -- 8-stage dual issue, in-order, superscalar processor with dual vector processing units (1024-bit VLEN/512-bit DLEN)
  • Highly customizable processor IP supporting the Lua scripting language
    • Native execution of the Lua scripting language
    • Build-time configurable
    • Run-time configurable
    • Each processor core is heterogeneous
    Block Diagram -- Highly customizable processor IP supporting the Lua scripting language
  • Sine Wave Frequency Generator
    • The Sine Wave Frequency Generator is a time and frequency aligned sine wave frequency generator allowing any frequency to be generated between 1Hz and 200kHz adjustable in 1Hz steps.
    • It uses the vendor's Adjustable Clock core as source for source synchronous frequency generation. It provides either a parallel DAC interface or a serial highly configurable SPI interface to access a DAC.
    Block Diagram -- Sine Wave Frequency Generator
  • Neuromorphic Processor IP
    • In-Memory Compute: Efficient analog MACs for AI workloads
    • Compact Footprint: 0.28 mm² including peripheral circuitry
    • Wishbone Interface: Easy integration with standard digital buses
    • Ready for Tapeout: Fully synthesized and foundry-compatible
    Block Diagram -- Neuromorphic Processor IP
  • Lowest Power and Cost End Point AI Accelerator
    • Up to 1 TOPS
    • Up to 1 MB Local Memory
    • RISC-V/Arm Cortex-M 32-bit CPU
    • 3 x AXI4, 128b (Host, CPU & Data)
    Block Diagram -- Lowest Power and Cost End Point AI Accelerator
  • Performance AI Accelerator for Edge Computing
    • Up to 16 TOPS
    • Up to 16 MB Local Memory
    • RISC-V/Arm Cortex-R or A 32-bit CPU
    • 3 x AXI4, 128b (Host, CPU & Data)
    Block Diagram -- Performance AI Accelerator for Edge Computing
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Semiconductor IP