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Search (13)
Compare 13 PowerPC IP from 6 vendors (1 - 10)
  • Customizable Video Input controller
    • CVI is a fully Customizable Video Input controller IP core.
    • The video input controller can be applied to e.g. FPGA systems with a resource optimized, application specific feature configuration or to ASIC projects applying a more generic feature set and thus more flexibility.
    Block Diagram -- Customizable Video Input controller
  • Customizable Display Controller IP
    • CDC is a fully Customizable Display Controller IP supporting up to 16k resolutions (4096x4096 pixel) on a MIPI-DPI compliant parallel video output.
    • Several features can be configured at synthesis time and programmed at run time.
    • The display controller can be applied to e.g. FPGA systems with a resource optimized, application specific feature configuration or to ASIC projects applying a more generic feature set and thus more flexibility.
    Block Diagram -- Customizable Display Controller IP
  • PowerPC Bus Arbiter
    • Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
    • Designed for ASIC or PLD implementations in various system environments.
    • Fully static design with edge triggered flip-flops.
    • Supports up to eight PowerPC bus masters with unlimited slave device support.
    Block Diagram -- PowerPC Bus Arbiter
  • PowerPC to PCI Bridge
    • Fully supports PCI specification 2.1 and 2.2 protocol.
    • Designed for ASIC and PLD implementations.
    • Fully static design with edge triggered flip-flops.
    • Supports all PowerPC CPU with 603 bus interface and MPC860 interface.
    Block Diagram -- PowerPC to PCI Bridge
  • PowerPC Bus Slave
    • Fully supports PowerPC 60x bus protocol including PowerPC 603, 604, 740, 750 and MPC8260.
    • Designed for ASIC or PLD implementations in various system environ-ments.
    • Fully static design with edge triggered flip-flops.
    • Direct support for standard asynchronous SRAM and synchronous BURST SRAM.
    Block Diagram -- PowerPC Bus Slave
  • PowerPC Bus Master
    • Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
    • Designed for ASIC or PLD implementations in various system environments.
    • Fully static design with edge triggered flip-flops.
    • Automatic bus arbitration for address bus and data bus based on internal bus request.
    Block Diagram -- PowerPC Bus Master
  • Display Controller – LCD / OLED Panels (Avalon Bus)
    • The DB9000AVLN TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the Avalon Bus within Altera Qsys Integration (generating the System Interconnect Fabric) to a TFT LCD panel.
    • In an Altera FPGA, typically, the microprocessor is a NIOS II or ARM processor and frame buffer memory is either on-chip SRAM memory or larger off-chip SRAM or SDRAM.
    Block Diagram -- Display Controller – LCD / OLED Panels (Avalon Bus)
  • Display Controller – Ultra HD LCD / OLED Panels (AXI4/AXI Bus)
    • The DB9000AXI4-UHD LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Interconnect to an 4K/8K TFT LCD / OLED display panel.
    • The video image in frame buffer memory can be 8/10/12-bit 4:2:0 or 4:2:2 or 4:4:4 sampled YCrCb video or 4:4:4 RGB. For 4:2:0 and 4:2:2 YCrCb, the chroma components are re-sampled to 4:4:4 and color converted to RGB.
    Block Diagram -- Display Controller – Ultra HD LCD / OLED Panels (AXI4/AXI Bus)
  • Motorola MC6845 Functional Equivalent CRT Controller
    • The DB6845 CRT Controller core is a full function equivalent to the Motorola MC6845 device.
    • The DB6845 interfaces a microprocessor to a raster-scan CRT display. The microprocessor access 19 registers (1 Address and 18 Data Registers) within the DB6845 in order to provide video timing, refresh memory addresses, cursor, and light pen strobe signals.
    • CRT video timing signals include Vertical Sync (VS), Horizontal Sync (HS), and Display Enable (DE) output signals. Refresh memory addressing includes Memory Address (MA[13:0]) and Row Address (RA[4:0]) output buses.
    Block Diagram -- Motorola MC6845 Functional Equivalent CRT Controller
  • BitBLT Graphics Hardware Accelerator (Avalon Bus)
    • The DB9100AVLN BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to combining existing bitmaps on and off-screen using one of 256 Raster Operations.
    • A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT).
    Block Diagram -- BitBLT Graphics Hardware Accelerator (Avalon Bus)
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