IP Catalog > Analog IP

Analog IP

Analog IP generally handles every feature on a chip that connects to the outside world, plus power management and clocking.

Analog IP cores in this category include PLLs that generate various clocks, A/D converter IP and D/A converter IP that convert analog and digital signals, sensor IPs that measure temperature and voltage, and analog functional parts for configuring analog front ends (AFEs).

Explore our vast directory of Analog IP cores below.

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Search (5,510)
Compare 5,510 Analog IP from 120 vendors (1 - 10)
  • Crystal Oscillators
    • The crystal oscillator macros are available in a wide range of industry-standard quartz crystals and MEMS resonators operating in the fundamental mode in the 32 kHz to 80 MHz range.
    • These oscillators, which are both power and area efficient, have a programmable transconductance to allow users to find the optimal balance between jitter and power consumption.
    Block Diagram -- Crystal Oscillators
  • PVT Sensor on INTEL 16
    • The PVT Sensor is a highly integrated macro for monitoring process, voltage, and temperature variation on-chip, allowing very high precision even in untrimmed usage.
    • It consumes very little power even in operational mode, and leakage power only when measurement is complete.
    Block Diagram -- PVT Sensor on INTEL 16
  • 4-Phase LC PLL on INTEL 16
    • High performance design for meeting low jitter requirements including Ref Clock applications
    • Implemented with Analog Bits’ proprietary LC architecture
    • Low power consumption
    • Integrated power supply regulation for low deterministic jitter
    Block Diagram -- 4-Phase LC PLL on INTEL 16
  • 18-40MHz Crystal Oscillator on INTEL-16
    • Crystal Oscillator pad macro that supports many industry standard crystals in the 18-40MHz range (e.g. 19.2, 24MHz, 25MHz, 38.4MHz)
    • Uses standard CMOS transistors
    • Crystal Oscillation Mode: Fundamental
    • Power down option for IDDQ testing
    Block Diagram -- 18-40MHz Crystal Oscillator on INTEL-16
  • Ultra-low power RF receiver / WakeUp receiver
    • Supply current: < 3 uA @ 1.8 V (1 kbit/s)
    • Response time: < 30 ms (1 kbit/s)
    • Sensitivity: -80 dBm
    Block Diagram -- Ultra-low power RF receiver / WakeUp receiver
  • Ultra-Low-Power 6-13 Bit 0.5-10 KS/s 10μW Analog-Frontend on XFAB XT018
    • The Analog-Frontend (AFE) IP consists of programmable current and voltage preamplifier followed by a Successive Approximation Register (SAR) architecture ADC using charge-redistribution technique.
    • The ADC IP is configurable regarding resolution (6-13 bit) and sample rate (up to 10kS/s). The preamplifier offers programmable gain from 0.5 to 4. The input voltage range is quasi-rail-to-rail guaranteeing more than +- 1.7 V @ 1.8 V power supply. An optional calibration technique can be applied to compensate degraded mismatch behavior of technology capacitors.
    • The overall power consumption of the AFE IP sums up with 10.5 uW at 1 kHz input signal.
    Block Diagram -- Ultra-Low-Power 6-13 Bit 0.5-10 KS/s 10μW Analog-Frontend on XFAB XT018
  • 8 Bit 6 GS/s Current Steering DAC on Fujitsu 55 nm CS250L
    • The IP consists of an 8 bit current steering DAC clocked externally for 4 - 6 GS/s. The differential output signal of maximum +/- 800 mV is driven onto a load impedance of 100 Ohm and can be calibrated within a range of +/- 25 % of its nominal value to adjust to load conditions.
    • The IP needs an external clock with high accuracy and low periodic jitter, because the clock jitter influences the dynamic behavior of the converter.
    Block Diagram -- 8 Bit 6 GS/s Current Steering DAC on Fujitsu 55 nm CS250L
  • 12-Bit 1 MS/s DAC with voltage output on AMS C18
    • Resolution: 12 bit
    • Conversion rate: 1 MS/s
    • Power consumption: 15 mW @ 3.3 V
    Block Diagram -- 12-Bit 1 MS/s DAC with voltage output on AMS C18
  • 11 Bit 100 kS/s Ultra-Low Power SAR ADC on GlobalFoundries 22FDSOI
    • The ADC IP is a general-purpose successive approximation converter for low-power medium resolution applications. Sample rate, resolution and power consumption are configurable.
    • It is built using typical differential capacitor-DAC architecture, clocked comparator and bootstrapped switches. No additional reference voltage is required, achieving lmost rail-to-rail input. The target applications are environmental and biomedical signal processing.
    Block Diagram -- 11 Bit 100 kS/s Ultra-Low Power SAR ADC on GlobalFoundries 22FDSOI
  • 12 Bit 20 MS/s Pipeline ADC on XFAB XH035
    • This pipelined ADC can be applied for up to 20MSps sampling frequencies. By using interleaved switched-capacitor circuitries a CLK signal with half the sampling rate needs to be applied.
    • This ADC is built as a single-ended architecture and is designed to convert input signals from 0.5 – 2.3V at 3.3V supply voltage with up to 10 MHz input bandwidth with 12 bits resolution.
    Block Diagram -- 12 Bit 20 MS/s Pipeline ADC on XFAB XH035
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