Analog IP
Analog IP generally handles every feature on a chip that connects to the outside world, plus power management and clocking.
Analog IP cores in this category include PLLs that generate various clocks, A/D converter IP and D/A converter IP that convert analog and digital signals, sensor IPs that measure temperature and voltage, and analog functional parts for configuring analog front ends (AFEs).
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Analog IP
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5,585
Analog IP
from 123 vendors
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Core Powered Wide Range Programmable Integer PLL on TSMC CLN2P
- Electrically Programmable PLL with Fractional-N divide and Spread Spectrum Clock Generation
- Entirely core voltage powered, needs no analog supply voltage
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Very fine precision: near 1 part per billion resolution
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18-40MHz Crystal Oscillator on TSMC CLN2P
- Crystal Oscillator pad macro that supports industry standard crystals
- Uses standard CMOS transistors
- Crystal Oscillation Mode: Fundamental
- Power down option for IDDQ testing
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Ramping 12-bit ADC with Sequencer
- TSMC180 process
- Small Area: 0.21mm^2
- -40 to 125 Deg C
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Video DAC
- The Video DAC IP is designed for transmitting analog video signals from a video source device to a display device, which can be used to build many analog video interfaces, such as Composite (CVBS, AHD), S-Video (Y/C) and Component (YPrPb, RGB/VGA) video interfaces
- The Video DAC IP offers reliable implementation of analog video interfaces, which can be integrated in the SoCs used in multimedia devices
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10/12-bit SAR ADC
- The SAR ADC IP is a small-size, low power analog to digital converter which leverages charge-redistribution successive approximation technology
- It offers a reliable solution of analog-to-digital signal conversion for general application
- Innosilicon SAR ADC IP consists of input MUX, ADC core, and digital logic
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Process/Voltage/Temperature Sensor
- The PVT Sensor IP is designed for on-chip monitoring of processes, voltage, and temperature variations
- It is a critical component in modern SoC designs, enabling real-time measurement and monitoring of environmental and operational conditions
- It offers a reliable solution for chip operating condition monitoring applications, such as power supply IR drop measurement, high temperature alert, and dynamic performance adjustment
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Power-On-Reset IP
- The Power-On-Reset (POR) IP provides reliable reset functions for general applications
- It is powered by analog supply and monitors both analog and digital supply
- The POR IP generates a POR signal to reset the digital logic
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PLL
- The high performance PLL is a high speed, low jitter frequency synthesizer, developed as an IP block to reduce time to market, risk, and cost in the development of Analog Front-End design
- It can generate a stable high-speed clock from an ultra-wide input clock
- With excellent supply noise immunity, the PLL is ideal for use in noisy mixed signal SoC environments
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Master/Slave DLL
- The (Delay-Locked Loop) DLL PHY is a mix-signal circuit used in low-power and high-speed applications to align and synchronize clock signals with precise timing
- This IP ensures robust timing, minimizes skew, and operates efficiently with a small silicon footprint
- The DLL PHY is designed to generate precise phase-shifted clocks (e.g
- 0 ° , 90 ° , 180 °, 270 °) based on a reference clock, enabling high-speed data capture and transmission
