IP Catalog > Analog IP

Analog IP

Analog IP generally handles every feature on a chip that connects to the outside world, plus power management and clocking.

Analog IP cores in this category include PLLs that generate various clocks, A/D converter IP and D/A converter IP that convert analog and digital signals, sensor IPs that measure temperature and voltage, and analog functional parts for configuring analog front ends (AFEs).

Explore our vast directory of Analog IP cores below.

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Search (5,722)
Compare 5,722 Analog IP from 112 vendors (1 - 10)
  • 1.7GHz Multiplying PLL on TSMC 28nm
    • Including Loop-filter
    • VCO operating range : 850MHz - 1700 MHz
    • Output frequency range : 850MHz -1700 MHz
    • Input frequency range : 9.6MHz - 216MHz
    Block Diagram -- 1.7GHz Multiplying PLL on TSMC 28nm
  • 5GHz Multiplying PLL on TSMC 28nm
    • Including Loop-filter
    • VCO operating range : 2500MHz - 5000 MHz
    • Output frequency range : 1250MHz - 2500 MHz
    • Input frequency range : 12MHz - 320 MHz
    Block Diagram -- 5GHz Multiplying PLL on TSMC 28nm
  • 1.8GHz SSCG PLL on TSMC 28nm HPC+
    • Including Loop-filter
    • VCO operating range : 900MHz - 1800 MHz
    • Output frequency range : 900MHz-1800 MHz
    • Input frequency range : 12MHz - 192MHz
    Block Diagram -- 1.8GHz SSCG PLL on TSMC 28nm HPC+
  • 3.2GHz SSCG PLL on TSMC 12nm
    • Including Loop filter
    • VCO operating range : 1600MHz- 3200MHz
    • Output frequency range: 400MHz- 3200MHz
    • Input frequency range : 10MHz- 200MHz
    Block Diagram -- 3.2GHz SSCG PLL on TSMC 12nm
  • 4.3GHz SSCG PLL on TSMC 7nm
    • Including Loop filter
    • VCO operating range : 2000MHz-4300MHz
    • Output frequency range: 500MHz-4300MHz
    • Input frequency range : 10MHz- 200MHz
    Block Diagram -- 4.3GHz SSCG PLL on TSMC 7nm
  • Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
    • TSMC IP9000 Alliance member enabling automotive IP support in TSMC automotive processes
    • Automotive Documentation including Safety Manual, FMEDA and DFMEA
    • Design reliability report containing EM/IR and Aging analysis
    Block Diagram -- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
  • General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
    • This Integer-N Hybrid (Digitally Aided Analog) PLL generates clock signals within broad frequency range.
    • Division coefficients of the embedded input and feedback dividers can be set to any integer between 1 and 64 or may be bypassed to save power.
    • Higher order dividers and/or pre-scalers are optional.
    Block Diagram -- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
  • 32Gbps, 31 order, Pseudo Random Bit Sequence Generator / Checker
    • This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps. Error count is accurate: no double counts or omissions regardless of error sequence or frequency of occurrence.
    • Can be used as Generator, Checker or both. No inductors are used minimizing area and EM interference. Simple control interface, with low frequency asynchronous signals only.
    Block Diagram -- 32Gbps, 31 order, Pseudo Random Bit Sequence Generator / Checker
  • 32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator/Checker
    • PRBS order: 7, 15 or 31 based on formulas: X1=X6^X7; X1=X14^X15; X1=X28^X31
    • Full bit rate at input and output up to 32Gbps
    • Generator, Checker and Counter functions
    • Accurate error count: no omissions or double counts
    • Full rate CMOS differential input data, centered with half-rate CMOS differential clock
    • Full rate CMOS differential output data, aligned with half-rate CMOS differential clock
    Block Diagram -- 32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator/Checker
  • All Digital Fractional-N PLL for Performance Computing in UMC 40LP
    • Fractional multiplication with frequency up to 4GHz
    • Low jitter (< 10ps RMS)
    • Small size  (< 0.01 sq mm)
    • Low Power (< 5mW)
    Block Diagram -- All Digital Fractional-N PLL for Performance Computing in UMC 40LP
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