MIPI IP
MIPI IP cores enable seamless communication between processors, sensors, and peripherals in mobile, automotive, and consumer electronics applications. Two key components of MIPI IP cores are the MIPI Controller IP and MIPI PHY IP. The MIPI Controller IP manages the data transfer process, ensuring efficient and reliable communication between devices, while the MIPI PHY IP handles the physical layer of the interface, ensuring high-speed, noise-resistant signal transmission.
Explore our vast directory of MIPI IP cores below.
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MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- Technology is TSMC 22nm ULP 1p10M.
- Supply voltage can be applied 1.0V for core voltage, 1.8V for IO voltage.
- Maximum data rate of each channel is 1.5Gbps at High-speed mode for MIPI D-PHY Transmitter.
- Data rate of each channel is 609Mbps for FPD-Link(LVDS).
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MIPI D-PHY Transmitter/Receiver for DSI/CSI-2 on Samsung 28nm FD-SOI
- Technology is Samsung 28nm FD-SOI 8M (6U1x_2T8x_LB).
- Supply voltage can be applied 1.1V for core voltage, 1.8V for IO voltage.
- Maximum data rate of each channel is 1.5Gbps at High-speed mode.
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MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP
- Renesas MIPI D-PHY Transmitter/Receiver can be used for analog Transmitter/Receiver of following interface.
- Technology is TSMC 40nm LP 1p6M (4x1z) .
- Supply voltage can be applied 1.1V for core voltage, 1.8V for IO voltage.
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MIPI C/D-PHY Combo IP
- Compliant to MIPI D-PHY v3.0, C-PHY v2.1 specification
- Area efficient macro optimized for placement for dense SoC designs
- Support Uni-(TX or RX) and Bi-directional(TX and RX) mode
- Support emphasis architecture over lossy channel for TX
- Support equalize architecture over lossy channel for RX
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DSI-2 TX/RX Controller
- DSI-2 TX/RX IP supports both transmit and receive functions in line with the DSI-2 v1.1 and D-PHY v2.0 standards.
- Designed for modern SoCs integrating display functionality, it supports high-speed and low-power modes, lane configurability, and robust link features—making it ideal for advanced embedded display applications.
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MIPI CSI-2 RX Controller
- Lane merging, virtual channel detection, and programmable data extraction
- Error detection and correction, including packet-level and protocol decoding errors
- Supports all pixel formats defined in the CSI-2 standard
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Simulation VIP for MIPI CSI-2
- Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
- Generates constrained-random bus traffic with predefined error injection at CSI-2, D-PHY, C-PHY and A-PHY levels
- Callbacks access at multiple TX and RX queue points for scoreboarding and data manipulation
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Simulation VIP for MIPI M-PHY
- Specification Compliance
- Complies with MIPI M-PHY 4.0, 4.1 and 5.0 specification
- M-PHY Type 1 and Type 2
- Supports Type 1 and Type 2
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Simulation VIP for MIPI UniPro
- Compliance: Contains predefined checks to verify that the DUT agents adhere to the protocol rules
- Error detection: Supports error detection on all layers, more than 240 different protocol checks
- Coverage: Monitors, checks, and collects coverage on bus traffic using hundreds of automatic protocol checks, including configuration and runtime checks
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MIPI SoundWire I3S Manager IP
- The MIPI SoundWire I3S Manager IP enables efficient, low-power, and high-fidelity audio data transfer for mobile, consumer, and automotive applications.
- Compliant with the MIPI SoundWire I3S (Inter-IC Sound) standards, it supports synchronized, multi-channel audio over a scalable two-wire interface, ideal for connecting digital microphones, amplifiers, and codecs in space-constrained designs.
