MIPI IP
MIPI IP cores enable seamless communication between processors, sensors, and peripherals in mobile, automotive, and consumer electronics applications. Two key components of MIPI IP cores are the MIPI Controller IP and MIPI PHY IP. The MIPI Controller IP manages the data transfer process, ensuring efficient and reliable communication between devices, while the MIPI PHY IP handles the physical layer of the interface, ensuring high-speed, noise-resistant signal transmission.
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MIPI IP
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MIPI CSI-2 IP
- The MIPI CSI-2 IP core is a highly scalable and silicon-agnostic implementation of the MIPI Camera Serial Interface 2 version 4.1 targeting ASIC and FPGA technologies.
- The MIPI CSI-2 implementation enables high-speed, low-power transmission of image data from camera modules to host processors.
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Mipi Unipro Verification IP
- MIPI UniPro VIP is fully compliant with MIPI UniPro Specification 2.0 and MIPI M-PHY Specification 5.0
- Fully supports Transport Layer, Network Layer, Data Link Layer, PHY Adapter Layer and Device Management Entity
- Supports maximum of four Lanes in each direction
- Supports different HS-GEAR or PWM-GEAR in both directions.
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MIPI M-PHY Verification IP
- Compliant to MIPI M-PHY Version 5.0
- Supports two SUB-LINKs with configurable number of LANEs in each
- Supports high speed and low speed modes for all modules
- Supports HS-BURST with all HS-GEARs, HS-G1 to HS-G3 in HS-MODE
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MIPI DSI v2.2 Verification IP
- Compliant to MIPI DSI Specification version 2.2 and MIPI C-PHY Specification version 2.1 with PPI interface.
- Support all Calibration Format & operations
- C-PHY supports MFAA and SFAA for DSI TX and RX respectively for Data Lane Module in command mode.
- C-PHY supports MFAN and SFAN for DSI TX and RX respectively for data Lane Module in video mode.
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MIPI DSI v1.3.2 Verification IP
- Compliant to MIPI DSI Specification version 1.3.2 and MIPI D-PHY Specification version 1.2 with PPI interface.
- Support all Calibration Formats & operations
- D-PHY supports MFAA and SFAA for DSI TX and RX respectively for Data Lane Module in command mode.
- D-PHY supports MFAN and SFAN for DSI TX and RX respectively for Data Lane Module in video mode.
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MIPI D-PHY Verification IP
- Compliant to MIPI D-PHY Specification Version 3.5 with PPI interface.
- Support HS-IDLE State between two data burst.
- Support for Alternate calibration Sequence & Preamble sequence.
- Supports all possible configuration for Data Lane Module and Clock Lane Module at PHY layer.
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MIPI CSI-2 with C-PHY Verification IP
- Compliant to MIPI CSI-2 Specification Version 4.0.1 along with MIPI C-PHY Specification Version 2.1 with PPI interface
- Supports upto 32 virtual channels with C-PHY
- C-PHY supports MFEN and SFEN for CSI-2 TX and RX respectively for Data Lane greater than 1
- C-PHY supports MFAA and SFAA for CSI-2 TX and RX respectively for Data Lane 1 module
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MIPI CSI-2
- Fully MIPI CSI-2 standard compliant
- 64 and 32-bit core widths
- Transmit and Receive versions
- Supports 1-8, 9.0+ Gbps D-PHY data lanes
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MIPI DSI2
- Fully MIPI DSI-2/DSI standard compliant
- 64 and 32-bit core widths
- Host (Tx) and Peripheral (Rx) versions
- Supports 1-4, 9.0+ Gbps D-PHY data lanes
- Supports 1-4, 6.0+ Gsym/s C-PHY lane (trio)
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MIPI M-PHY
- The M-PHY implements MIPI M-PHY protocol V4.1
- The M-PHY protocol specification is a part of a group of communication protocols defined by MIPI® Alliance standards intended for mobile system chip to chip communications
- The M-PHY specification is specifically designed to be suitable for multiple protocols and for a wide range of applications
