DPA and FIA Countermeasures IP

The FPGA Lock is a small FPGA IP core that uses the $0.52 Microchip ATSHA204A hardened crypto authentication IC and one FPGA pin to lock down FPGAs and hardwareto stop IP theft and prevent CEM hardware counterfeiting.

• 1. AMBA-AXI-4.0 Master and Slave
• 2. Blocks user to snoop the meaningful data.
• 3. Block User from SPA/ DPA Gassing the secure data.
• 4. End to End ECC Secured transactions.

• 1. AMBA-AHB Master and Slave
• 2. Blocks user to snoop the meaningful data.
• 3. Block User from SPA/ DPA Gassing the secure data.
• 4. End to End ECC Secured transactions.

• Adaptability for consumer requirements
• Product are customized based on customer requests
• Low latency
• Tunable in terms of:

• The SCA-resistant AES-IP-3X family of crypto accelerator cores provide semiconductor manufacturers with superior AES cipher acceleration.
• The cores are easily integrated into ASIC/SoC and FPGA devices and offer a high-level of resistance to various Side Channel Attacks like Differential Power Analysis (DPA), and optionally offer detection of Fault Injection Attacks (FIA).

• Texplained’s countermeasure is schematically composed of two main blocs:
• 1. The Detection Module detects the attack « on the fly »
• => Its checks the execution flow of the software to detect if a Hardware attack is in progress
• 2. The Defense Module reacts to the attack by preventing the striker to obtain the code in the NVW