IP Catalog > Analog IP > Power Management IP

Power Management IP

Power management IPs are indispensable in modern chip design, especially for battery applications where power is constrained and for high-power applications where thermal efficiency is vital. Power management IPs are specialized blocks or circuits that help to control the power consumption, voltage levels and energy efficiency of a system.

Power Management IP, such as Low Drop-Out (LDO) Regulators, Power-On-Reset (POR) Monitors, and the Power Management Unit (PMU) Subsystem, ensure low power consumption with optimal performance.

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Search (921)
Compare 921 Power Management IP from 51 vendors (1 - 10)
  • 16mA 4V Voltage Regulator on XFAB XT018
    • The TS_VR_4V00_X8 is a 4V voltage regulator capable of delivering up to 16mA. It is required for the supply of other TES IPs like TS_FS_9M70_X8,
    • TS_VA_LNDC_X8, and TS_CS_20uA_X8. The TS_VR_4V00_X8 operates with one supply voltage, VDDA5, VDDIO (5V typical) and one precision reference voltage VREF (2.5V).
    Block Diagram -- 16mA 4V Voltage Regulator on XFAB XT018
  • 50mA 1.8V Voltage Regulator with Power-Good Signal on XFAB XT018
    • The TS_VR_1V8_X8 is a 1.8V linear voltage regulator (LDO) designed to supply the digital core of an ASIC.
    • The LDO operates with an input voltage of 3.3V (supply voltage) and provides a regulated output voltage of 1.8V.
    • It can provide a maximum DC load current of up to 50mA.
    Block Diagram -- 50mA 1.8V Voltage Regulator with Power-Good Signal on XFAB XT018
  • 10mA 3.3V Low-Dropout (LDO) Regulator on XFAB XT018
    • The TS_VR_3V3_X8 is a 3.3V low-dropout linear regulator (LDO) to supply the digital core of an analog ASIC.
    • The LDO operates with an input voltage of 5V (supply voltage) and provides an output regulated voltage of 3.3V.
    • The LDO can supply a maximum DC load current of 10mA.
    Block Diagram -- 10mA 3.3V Low-Dropout (LDO) Regulator on XFAB XT018
  • Power-OK Monitor
    • The agilePOK is a Power OK monitor that consists of a voltage reference and comparators to set a programmable high and low threshold level for power supply integrity detection.
    • The number of trigger outputs can be customized and each threshold can be adjusted during operation to support DVFS operation.
    • This monitor can be used to detect loss of power or attacks to the power supply.
    Block Diagram -- Power-OK Monitor
  • Power on Reset 1.2V
    • SMIC 55nm LL technology
    • Noise protected
    • Low current consumption (~1uA)
    Block Diagram -- Power on Reset 1.2V
  • Retention Alternative Regulator, combines a linear regulator and an ultra-low quiescent regulator for sleep mode
    • Ideal regulator for power and voltage islets
    • Secured integration in the SoC Embedded RCU (Regulator Control Unit) to manage booting and mode transitions and to ensure data integrity
    • Configurable output drive before delivery to fit the application
    • Performances in sleep mode: qLR with low quiescent current: 0.2 uA
    Block Diagram -- Retention Alternative Regulator, combines a linear regulator and an ultra-low quiescent regulator for sleep mode
  • Linear Regulator, ultra low quiescent current for retention mode TSMC 40uLPeF
    • qLR-Aubrey-ref-1.62-3.63-0.55-2.5.02_TSMC_40_uLPeF is an ultra-low quiescent LDO (Linear regulator) in TSMC 40uLPeF.
    Block Diagram -- Linear Regulator, ultra low quiescent current for retention mode TSMC 40uLPeF
  • Linear Regulator, ultra low quiescent current for retention mode
    • Very low quiescent and leakage for Low-Power
    • Retention capability enables optimization of the power consumption depending on the modes and needs of the SoC
    • Can supply always-on very low loads
    • Low Bill-of-Material: supports external capacitor if required by the system
    Block Diagram -- Linear Regulator, ultra low quiescent current for retention mode
  • Combined Power-On-Reset and Brown-Out-Reset in TSMC 22ULL
    • Can be used to monitor 3.3V battery or voltage regulator output
    • Monitored input voltage programmable from 0.55V to 3.3V
    • Dual POR and BOR functions
    • Low power mode for best consumption in sleep mode
    Block Diagram -- Combined Power-On-Reset and Brown-Out-Reset in TSMC 22ULL
  • Low input voltage high performance LDO regulator in TSMC 22ULL
    • LDO-T22-1-1.8-0.6-1.05_TSMC_22_ULL is a Low input voltage, high performance LDO linear regulator in TSMC 22ULL with programmable output voltage to supply core logic domains, SRAM arrays or RF/analog domains.
    • It features normal and low-power (LP) operating modes to adjust the amount of output current depending on the application requirements.
    Block Diagram -- Low input voltage high performance LDO regulator in TSMC 22ULL
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