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Compare 78 Other from 32 vendors (1 - 10)
  • ARINC 429 IP Core
    • Supports ARINC 429 Specification
    • Configurable up to 32 Rx and 16 Tx Channels
    • Supports 12.5 kbit/s and 100kbit/s data rates
    Block Diagram -- ARINC 429 IP Core
  • Intra-Panel Multi Standard TX PHY 14nm
    • COG and COF transmitter
    • Data Rate : 120M ~ 3.6Gbps
    • Power-down mode
    Block Diagram -- Intra-Panel Multi Standard TX PHY 14nm
  • Highly configurable high-speed serial link controller
    • SpaceFibre codec designed according to the SpaceFibre specification ECSS-E-ST-50-11C, single-lane implementation
    • WizardLink codec designed to interface with Texas Instrument TLK2711 transceiver
    • The IP can inter-operate with off-chip SerDes devices or with FPGA/ASIC hard macros
    • Optional 8b10b encoding
    Block Diagram -- Highly configurable high-speed serial link controller
  • Spacewire Codec with AHB host interface
    • Full implementation of Spacewire standard
    • Protocol ID extension ECSS-E-50-12 part 2
    • Optional RMAP protocol draft C
    • AMBA AHB back-end with DMA
    Block Diagram -- Spacewire Codec with AHB host interface
  • ARM HSSTP PHY with Link Layer
    • ARM HS-STP v6.0
    • ARM Coresight DDI 0314H
    • Xilinx Aurora 8b/10b v2.2
    Block Diagram -- ARM HSSTP PHY with Link Layer
  • ARINC 429 IP Core
    • Multichannel module supporting ARINC429 Receiver/Transmitter.
    • Configurable module supporting any number of receivers and transmitters (Standard with 16 receivers & 8 transmitters).
    • Configurable data rate supporting from 12.5 Kbps to 1 Mbps.
    • Parity & Gap generators & checkers for high data integrity.
    Block Diagram -- ARINC 429 IP Core
  • SerialLite PHY with PCS
    • Integrated PCS Layer
    • Low power & area
    • Test Silicon
    Block Diagram -- SerialLite PHY with PCS
  • CEI-6G-SR PHY
    • Low Risk
    • Excellent Interoperability
    • Superior Noise Immunity
    Block Diagram -- CEI-6G-SR PHY
  • XAUI PHY
    • Very low output jitter
    • Receiver equalization for enhanced jitter tolerance
    • Programmable TX levels with multiple post-cursor emphasis options
    • Automatic driver/receiver impedance calibration
    Block Diagram -- XAUI PHY
  • SMBUS Slave IIP
    • Compliant with SMBus version 3.1 specification.
    • Full SMBus Slave Functionality
    • Supports Clock stretching to insert wait states
    • Supports command code Protocols
    Block Diagram -- SMBUS Slave IIP
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Semiconductor IP