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PMBus Verification IP
- Fully compliant with Rev. 1.4 of the PMBus Specification.
- Support for all SMBus protocols with and without PEC (Packet Error Checking).
- Support for SMBus ARP (Address Resolution Protocol) for dynamically assigning a unique address to each slave device.
- Support Group command protocol for multiple PMBus device communication.
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RTC Verification IP
- Compliant to RTC basic specification as defined in DS3234 maxim_spi_rtc
- Supports configurable timing parameters and multi-slave configurations.
- Supports multi-slave memory.
- Supports Master and Slave Mode.
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SMBus Verification IP
- Fully compliant with Rev. 3.1 of the SMBus Specification
- Support PEC (Packet error Checking) for communication robustness.
- Support for all Bus protocols with and without PEC.
- Support for SMBus ARP (Address Resolution Protocol) for dynamically assigning a unique address to each slave device.
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SPI/xSPI/QSPI/OSPI Verification IP
- The SPI/xSPI/QSPI/OSPI Verification IP provides an effective & efficient way to verify the components interfacing with SPI/QSPI/OSPI interface of an ASIC/FPGA or SoC.
- VIP environment encapsulates the SPI/xSPI/QSPI/OSPI compatible UVM based Master, compatible Slave, BUS monitor & Scoreboard.
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UART/USART Verification IP
- Available in UVM, System UVM, UVM.
- According to the National Semiconductor PC16550D Compliance.
- Supports Simplex and Duplex mode.
- Independently controlled transmit, receive, line status, and data set interrupts
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LTTPR Verification IP
- Supports 8b/10b encoding and 128/132b encoding.
- LTTPR is compliant with DP1.4, DP2.0, and DP2.1.
- DisplayPort VIP Supports Singe as well as Multi LTTPR environment.
- LTTPR supports FEC encoding and decoding.
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OTL Verification IP
- The OTL Verification IP Product is the comprehensive OTL interface protocol validation solution.
- ITU-T recommendation G.709 annexure C defines OTL interface mechanism by which OTU4 and OTU3 signals can be car ried for short-reach client side applications.
- OTU4 signals can be carried over 10 parallel lanes, which are formed by bit multiplexing of 20 logical lanes. OTU3 signals can be car ried over 4 parallel lanes.
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SLVS-EC Receiver IP
- SLVS-EC is the next-generation, high-speed interface for high-resolution CMOS image sensors.
- This standard is tolerant of lane-to-lane skew because of embedded clock technology that simplifies board-level design of high-speed and long-distance data transmission.
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SpaceWire link controller with SpaceWire RMAP support and AMBA host interface
- Full implementation of Spacewire standard
- Protocol ID extension ECSS-E-50-12 part 2
- Optional RMAP protocol draft C
- AMBA AHB back-end with DMA
