IP for UMC

Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
Designed for ASIC or PLD implementations in various system environments.
Fully static design with edge triggered flip-flops.
Supports up to eight PowerPC bus masters with unlimited slave device support.

Fully supports PowerPC 60x bus protocol including PowerPC 603, 604, 740, 750 and MPC8260.
Designed for ASIC or PLD implementations in various system environ-ments.
Fully static design with edge triggered flip-flops.
Direct support for standard asynchronous SRAM and synchronous BURST SRAM.

Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
Designed for ASIC or PLD implementations in various system environments.
Fully static design with edge triggered flip-flops.
Automatic bus arbitration for address bus and data bus based on internal bus request.

SMS6000 is a fully integrated CMOS transceiver that handles the low level Serial ATA protocol and signaling.
It contains all necessary Clock synthesis, Clock Recovery, Serializer, Deserializer, Comma detect for 8B/10B encoded data and Frame alignment functionalities.

Supports 2.5Gb/s serial data rate
Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
Data and clock recovery from serial stream on the PCI Express bus

The icyTRX ultra-low-power RF transceiver is designed to meet standards such as Bluetooth Low Energy (BLE), 802.15.4 PHY Layer (e.g. ZigBee), and proprietary standards with data rates from 62.5 kBit/s up to 4 Mbit/s.
icyTRX offers 5.3 mW consumption in receive mode from a 1.0 V supply. icyTRX is a complete transceiver that is designed for miniaturization, yielding an area of analog RF of less than 1 mm2 in 55 nm CMOS, requiring minimal external components thanks to high degree of integration. icyTRX is designed for easy integration into ASICs and SoCs.

Wide bus interface
Basic AES encrypt and decrypt operations
Key sizes: 128, 192 and 256 bits
Key scheduling in hardware, allowing key, key size and  direction changes every 13/15/17 clocks with zero impact  on throughput
Hardware reverse (decrypt) key generation

Compliant with the PCI Express 3.1/3.0, and PIPE (16- and 32-bit) specifications
Compliant with PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
Supports Endpoint, Root-Port, Dual-mode configurations
Supports x16, x8, x4, x2, x1 at 8 GT/s, 5 GT/s, 2.5 GT/s speeds
Supports AER, ECRC, ECC, MSI, MSI-X, Multi-function, P2P, crosslink, and other optional features
Supports many ECNs including LTR, L1 PM substates, etc.

The DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0 AXI System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.
The DB-I2C-M-AXI is a Master I2C Controller that controls the Transmit or Receive of data to or from slave I2C devices. Figure 1 depicts the system view of the DB-I2C-M AXI Controller IP Core embedded within an integrated circuit device.