IP for UMC

Every element of the eFPGA can be defined in numbers: logic cells, adaptive DSP (with and without FIR engine, add & mult size, amount), RAM (type and amount) and IOs.
In addition, Menta eFPGA IP Cores being 100% standard cells based, multiple power / performances trade-off can be achieved based on customer requirements.
The eFPGA IP Cores are provided as hard IPs (GDSII).
Menta eFPGA IP Cores use standard cells, and as such integrate smoothly into any standard ASIC design flow. Designers use RTL as the input to our software Origami Programmer to generate the eFPGA program file (bitstream) and obtain accurate performance evaluation.

Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
Input & output frequency ranges greater than 1000:1

Supports 2.5Gb/s serial data rate
Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
Data and clock recovery from serial stream on the PCI Express bus

Extends EV Driving range by 10%
Extends the driving and Biking Range of Electric Vehicles from 16 to 30 Miles
Occupies the same on chip area as standard DCAPs with at least a 600X effective capacitance increase
Up to a 36% Dynamic Power and RF Emissions Reduction