IP for UMC

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Compare 3,115 IP for UMC from 51 vendors (1 - 10)
  • Multiprotocol SerDes PMA
    • Supports over 30 protocols including CEI 6G & 11G SR, MR, LR, Ethernet 10GBASE-X/S/K/R, PCIe Gen1/2/3/4, V-by-One HS/US, CPRI, PON, OTN/OTU, 3GSDI, JESD204A/B/C, SATA1-3, XAUI, SGMII
    • Programmable (De)Serialization width: 8, 10, 16, 20, 32, or 40 bit
    • Tx ring PLL includes fractional multiplication, spread spectrum and Jitter Cleaner function for Sync-E and OTU
    • Core-voltage line driver with programmable pre-and post-emphasis
    Block Diagram -- Multiprotocol SerDes PMA
  • eFPGA Soft IP
    • These eFPGA IP cores offer designers the flexibility to tailor resources to their application requirements, available as either Soft RTL or Hard GDSII IP.
    • Our standard-cell-based approach facilitates rapid porting to new process geometries or variants, including industrial and rad-hard grade versions.
    Block Diagram -- eFPGA Soft IP
  • Complete USB Type-C Power Delivery IP
    • Mixed signal Analog Front End Macros for 65n, 130n, 150nm, and 180n technologies.
    • RTL code from AFE to I2C compatible register set.
    • Stand alone C code for Protocol, Device Policy Manager, and System Policy Manager.
    • IP demonstration & development board, with compliance reports. 
    • Full chip integration of USB Type-C, and associated software.
    Block Diagram -- Complete USB Type-C Power Delivery  IP
  • MIPI D-PHY Universal IP in UMC 28HPC+
    • Supports MIPI Alliance Specification for D-PHY Version 2.5
    • Consists of 1 Clock lane and 4 Data lanes
    • Embedded, high performance, and highly programmable PLL
    • Supports both low-power mode and high speed mode with integrated SERDES
    Block Diagram -- MIPI D-PHY Universal IP in UMC 28HPC+
  • Ultra low-power 2.4 GHz transceiver for Bluetooth Low Energy 5
    • Voltage supply: 1.3V down to 1V, with graceful degradation down to 0.9V
    • Compliant with direct operation from 1.2V battery
    Block Diagram -- Ultra low-power 2.4 GHz transceiver for Bluetooth Low Energy 5
  • MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
    • Dual mode PHY can support C-PHY and D-PHY
    • Supports MIPI Specification for D-PHY Version 1.2
    • Supports MIPI Specification for C-PHY Version 1.0
    Block Diagram -- MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
  • Dual 12-Bit 20 to 200MS/s 1.2V ADC, CMOS 90nm
    • TSMC 90nm general purpose 1.2V CMOS process
    • Single 1.2V supply
    • 20 to 200 Mspls/s scalable sampling rate
    • 0.5 Vp_diff input dynamic range
    Block Diagram -- Dual 12-Bit 20 to 200MS/s 1.2V ADC, CMOS 90nm
  • PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
    • Supports 2.5Gb/s serial data rate
    • Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
    • Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
    • Data and clock recovery from serial stream on the PCI Express bus
    Block Diagram -- PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
  • CC-100IP-MB Electric Vehicle Mileage Booster IP
    • Extends EV Driving range by 10%
    • Extends the driving and Biking Range of Electric Vehicles from 16 to 30 Miles
    • Occupies the same on chip area as standard DCAPs with at least a 600X effective capacitance increase
    • Up to a 36% Dynamic Power and RF Emissions Reduction
    Block Diagram -- CC-100IP-MB Electric Vehicle Mileage Booster IP
  • High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
    • Fractional-N digital PLL architecture, using an LC-tank oscillator
    Block Diagram -- High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
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