IP for UMC

The crystal oscillator macros are available in a wide range of industry-standard quartz crystals and MEMS resonators operating in the fundamental mode in the 32 kHz to 80 MHz range.
These oscillators, which are both power and area efficient, have a programmable transconductance to allow users to find the optimal balance between jitter and power consumption.

The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.

The MIPI M-PHY is a high-frequency low-power, Physical Layer IP that supports the MIPI^® Alliance Standard for M-PHY.
The IP can be used as a physical layer for many applications, connecting flash memory-based storage, cameras and RF subsystems, and for providing chip-to-chip inter-processor communications (IPC).

Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
Designed for ASIC or PLD implementations in various system environments.
Fully static design with edge triggered flip-flops.
Supports up to eight PowerPC bus masters with unlimited slave device support.

Fully supports PowerPC 60x bus protocol including PowerPC 603, 604, 740, 750 and MPC8260.
Designed for ASIC or PLD implementations in various system environ-ments.
Fully static design with edge triggered flip-flops.
Direct support for standard asynchronous SRAM and synchronous BURST SRAM.

Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
Designed for ASIC or PLD implementations in various system environments.
Fully static design with edge triggered flip-flops.
Automatic bus arbitration for address bus and data bus based on internal bus request.

SMS6000 is a fully integrated CMOS transceiver that handles the low level Serial ATA protocol and signaling.
It contains all necessary Clock synthesis, Clock Recovery, Serializer, Deserializer, Comma detect for 8B/10B encoded data and Frame alignment functionalities.

Supports 2.5Gb/s serial data rate
Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
Data and clock recovery from serial stream on the PCI Express bus

The icyTRX ultra-low-power RF transceiver is designed to meet standards such as Bluetooth Low Energy (BLE), 802.15.4 PHY Layer (e.g. ZigBee), and proprietary standards with data rates from 62.5 kBit/s up to 4 Mbit/s.
icyTRX offers 5.3 mW consumption in receive mode from a 1.0 V supply. icyTRX is a complete transceiver that is designed for miniaturization, yielding an area of analog RF of less than 1 mm2 in 55 nm CMOS, requiring minimal external components thanks to high degree of integration. icyTRX is designed for easy integration into ASICs and SoCs.