IP Catalog > Interface IP Cores > CPRI IP Cores

CPRI IP Cores

The CPRI IP cores implement the Common Public Radio Interface Specifications. CPRI is a high-speed serial interface for network radio equipment controllers (REC) to receive data from and provide data to remote radio equipment (RE).

Explore our vast directory of CPRI IP Cores below.

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Compare 22 CPRI IP Cores from 9 vendors (1 - 10)
  • eCPRI Altera® FPGA IP
    • The enhanced Common Public Radio Interface (eCPRI) Altera® FPGA IP core implements the eCPRI specification version 2.0
    • It is a front-haul interface protocol for radio base stations aimed at connecting the eCPRI Radio Equipment Control (eREC) and the eCPRI Radio Equipment (eRE) via front-haul transport network.
    Block Diagram -- eCPRI Altera® FPGA IP
  • CPRI Altera® FPGA IP
    • The Common Public Radio Interface (CPRI) Altera® FPGA IP core implements the CPRI Specification V7.0
    • CPRI is a high-speed serial interface for network radio equipment controllers (REC) to receive data from and provide data to remote radio equipment (RE)
    • The IP core targets high-performance, remote radio network applications
    • You can configure the CPRI Altera® FPGA IP core as an RE or an REC.
    Block Diagram -- CPRI Altera® FPGA IP
  • CPRI verification IP
    • The vendor provides configurable CPRI TX/RX verification IP
    • The CPRI verification IP is fully compatible with CPRI version v7.0 with backward compatibility to previous versions and provides an efficient and effective way to verify the component interfacing with CPRI interface of an IP
    Block Diagram -- CPRI verification IP
  • DiFi IP core
    • The DiFi IP core is a highly scalable and silicon agnostic implementation of the IEEE-ISTO Std 4900-2021: Digital IF Interoperability Standard v1.2.1 targeting ASIC, and FPGA technologies.
    • The DiFi implementation builds on long-time experience designing IP cores for sending and receiving Radio IQ data over Ethernet networks, and delivers a flexible engine that is prepared for tight integration with software applications.
    Block Diagram -- DiFi IP core
  • CPRI 7.0
    • The Common Public Radio Interface (CPRI) 7.0 core is a silicon agnostic implementation of the CPRI 7.0 specification, which is targeting both ASIC and FPGAs CPRI.
    • CPRI is a high-speed serial interface designed to meet or exceed the requirements of base band systems, C-RAN switches, Digital Front-End (DFE) processors or advanced test systems.
    • With its extreme flexibility and reduced logic consumption, the CPRI 7.0 IP core is the perfect match whether the application is REC (Radio Equipment Controller) or RE (Radio Equipment).
    Block Diagram -- CPRI 7.0
  • eCPRI
    • eCPRI core is a highly scalable and silicon agnostic implementation of the eCPRI standard targeting any ASIC or FPGA technologies.
    • The eCPRI implementation builds on Chip Interfaces long-time experience designing CPRI and Radio-Over-Ethernet solutions for fronthaul and delivers a flexible engine that is prepared for tight integration with software applications.
    Block Diagram -- eCPRI
  • CPRI 6.1
    • Common Public Radio Interface (CPRI) 6.1 core is a silicon agnostic implementation of the CPRI 6.1 specification, which is targeting both ASIC and FPGAs.
    • CPRI is a high-speed serial interface designed to meet or exceed the requirements of base band systems, C-RAN switches, Digital Front-End (DFE) processors or advanced test systems.
    Block Diagram -- CPRI 6.1
  • eCPRI Verification IP
    • Compliant with eCPRI Specification V2.0.
    • Complete eCPRI Tx/Rx functionality.
    • Supports the eCPRI layer of the eCPRI specification.
    • Supports 5G and enables increased efficiency.
    Block Diagram -- eCPRI Verification IP
  • CPRI Verification IP
    • Compliant with CPRI Specification V4.2/V5.0/V6.0/V6.1/V7.0
    • Complete CPRI Tx/Rx functionality.
    • Supports the Physical link layer (Layer 1) of the CPRI specification.
    • Supports different standard line bit rates of the CPRI specification
    Block Diagram -- CPRI Verification IP
  • CPRI Synthesizable Transactor
    • Compliant with CPRI Specification V4.2, V5.0, V6.0, V6.1 and V7.0.
    • Supports complete CPRI Tx/Rx functionality.
    • Supports the Physical link layer (Layer 1) of the CPRI specification.
    • Supports different standard line bit rates of the CPRI specification
    Block Diagram -- CPRI Synthesizable Transactor
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