Memory & Libraries IP
Welcome to the ultimate Memory & Libraries IP hub! Explore our vast directory of Memory & Libraries IP.
Memory & Libraries IP cores include a large listing of memory compilers, non-volatile memory (NVM), logic libraries, and IO solutions.
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Memory & Libraries IP
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4,335
Memory & Libraries IP
from 95 vendors
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ReRAM NVM in SkyWater 130nm CMOS
- Technology: 130nm, SkyWater S130
- Mask Adder: 2
- Supply Voltage: 1.8V Read, 1.8V+3.3/3.6V Program
- Read Access Time: <20nsec
- Operation Temp.: -40°C - 125°C (can be extended to -55°C)
- Capacity: 256 Kbit (can be customized for 128Kbit - 2Mbit)
- Data Bus Width (Read): 32-bit (can be customized to 16-bit to 128-bit)
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Ultra High-Speed Cache Memory Compiler
- Up to 3.4 GHz operation in N3P process
- Cache size up to 16 Kb
- 4 – 64-bit word width
- Configurable way associativity
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LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
- Compliant for JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
- x16 and x32 channel support
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CodaCache® Last Level Cache IP
- Standalone IP
- 1.2 GHz frequency in 16FF+TT process
- Protocol interoperability: AMBA AXI 4
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LVDS / sub-LVDS / DPHY TX - TSMC 6FFC
- The LVDS/Sub-LVDS/DPHY Combo TX converts parallel RGB data and 7/8/10 bits of CMOS parallel data into serial data streams.
- A phase-locked clock is transmitted in parallel with the data streams over a dedicated high-speed link.
- The polarity of differential signals for each data lane can be controlled.
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LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
- Process: Silterra 0.16um CMOS 1P5M Process
- Supply Voltage Range: AVDD33 = 3.3v +/-10%, AVDD18 = 1.8v +/-10%
- Ambient Temperature: 0°C~80°C
- Compatible with BLVDS_25 of Spartan-3A FPGA
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MIPI DPHY & LVDS Transmit Combo on GF55LPe
- MIPI D-PHY version 1.2 compliant PHY transmitter
- OpenLDI version 0.9 compliant LVDS transmitter
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Next Generation Flash device enabling small size, low power and direct connection with digital circuit which opens up new possibiities
- small size
- low power
- direct connection with digital circuit
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LPDDR5X/5/4X/4 combo PHY at 7nm
- Unbeatable performance-driven and low-power-driven PPA
- Ultra-low read/write latency with programmable PHY boundary timing
- Channel equalization with FFE and DFE
