Memory & Libraries IP
Welcome to the ultimate Memory & Libraries IP hub! Explore our vast directory of Memory & Libraries IP.
Memory & Libraries IP cores include a large listing of memory compilers, non-volatile memory (NVM), logic libraries, and IO solutions.
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IO Library - GLOBALFOUNDRIES 22FDX
- Library contains approx. 60 IO cells
- Support for all metal-stacks of 22FDX®
- Low voltage cells with nominal core voltages down to 0.4 V for glue-less interfacing to ULV Racyics® ABX digital standard cell domains
- Low leakage cells for ultra low power always-on domain usage
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Single Rail SRAM GLOBALFOUNDRIES 22FDX
- Ultra-low voltage logic designs using adaptive body biasing demand dense SRAM solutions which fully integrate in the ABB aware implementation and sign-off flow of the Racyics® ABX Platform solution.
- The Racyics® Single Rail SRAM supports ultra-low voltage operation down to 0.55 V where logic designs with Minimum-Energy-Point are implemented.
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Dual Rail SRAM Globalfoundries 22FDX
- Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
- Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABB
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1.2V Thin Oxide GPIO on TSMC 28nm RF HPC+
- The 1.2V Thin Gate GPIO is an IP macro for on-chip integration. It is a 1.2V general purpose I/O that does not rely on thick-gate devices. Only thin-gate, 0.9V capable core MOS devices are used in the design.
- Supported features include core isolation, programmable slew rate compensation, programmable drive strength, input/output enable, pull select and pull enable. Extra features such as programmable hysteresis can be supported upon request.
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3.3V Capable GPIO on TSMC 28nm RF HPC+
- The 3.3V capable GPIO is an IP macro for on-chip integration. It is a 3.3V general purpose I/O built with a stack of 1.8V thick oxide MOS devices. It is controlled by 0.9V (core) signals.
- Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
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1.8V Capable GPIO on Samsung Foundry 4nm FinFET
- The 1.8V capable GPIO is an IP macro for on-chip integration. It is a 1.8V general purpose I/O built with a stack of 1.2V MOS FINFET devices. It is controlled by 0.75V (core) signals.
- Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
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Flipchip 1.8V/3.3V I/O Library with ESD-hardened GPIOs in TSMC 12nm FFC/FFC+
- A 1.8V/3.3V flip-chip I/O library with ESD-immune GPIOs and integrated POC circuitry in TSMC FFC/FFC+.
- This library is a production-ready I/O library built on the TSMC 12nm process. The library features 1.8V to 3.3V GPIOs with programmable drive strength, hysteresis, and control logic.
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LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
- KA16UGLVDS01ST001 is a LVDS IO handling data rate up to 50Mbps with a maximum loading of 60pF.
- The differential voltage swing can be programmable from 0.35V to 1V.
- The output enable control function can be activated to decide the IO as input/output function. This IP also includes the IO PAD.
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Searchable Synchronous FIFO
- The FIFO-CAM controls are designed to operate over a wide range of clock frequencies.
- The interface signals are fully synchronous; no asynchronous signals are present on either side.
- Only reset may be asynchronous in that it may be asserted asynchronously and synchronized internally to the clock.
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Asynchronous FIFO with configurable flags and counts
- The aFIFO2 controls are designed to ensure hazard free clock domain crossing between the read and write ports.
- Only single control lines are re-synchronized between the two clock domains ensuring hazard free operation.
- The requirement for Gray coded addressing is thus eliminated. A wide range of clock frequencies and relative frequencies between read and write ports are fully tolerated.