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Memory & Libraries IP

Welcome to the ultimate Memory & Libraries IP hub! Explore our vast directory of Memory & Libraries IP.

Memory & Libraries IP cores include a large listing of memory compilers, non-volatile memory (NVM), logic libraries, and IO solutions.

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Search (4,022)
Compare 4,022 Memory & Libraries IP from 84 vendors (1 - 10)
  • GF 22FDX 5.5V OTP Auto-Grade1 IO Staggered
    • Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs
    • Synopsys’ embedded one-time programmable (OTP) non-volatile memory (NVM) IP, based on XHF architecture, enables designers to address these challenges
    • Synopsys’ OTP NVM IP architecture provides high levels of security, high yields, low power, and excellent reliability, which is why Synopsys OTP NVM is the leader in antifuse technology with >10B units shipped and availability in more than a dozen foundries
    • Synopsys OTP NVM IP is silicon-verified in TSMC N4P, N5, N5A, N6, and N7
    Block Diagram -- GF 22FDX 5.5V OTP Auto-Grade1 IO Staggered
  • GF 22FDX 5.5V OTP Auto-Grade1 IO Inline
    • Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs
    • Synopsys’ embedded one-time programmable (OTP) non-volatile memory (NVM) IP, based on XHF architecture, enables designers to address these challenges
    • Synopsys’ OTP NVM IP architecture provides high levels of security, high yields, low power, and excellent reliability, which is why Synopsys OTP NVM is the leader in antifuse technology with >10B units shipped and availability in more than a dozen foundries
    • Synopsys OTP NVM IP is silicon-verified in TSMC N4P, N5, N5A, N6, and N7
    Block Diagram -- GF 22FDX 5.5V OTP Auto-Grade1 IO Inline
  • Library of LVDS IOs cells for TSMC 40LP
    • TSMC 40 LP
    • 2.5V/1.1V IO/Core transistors
    • Fully compliant with TIA/EIA-644-A-2001
    Block Diagram -- Library of LVDS IOs cells for TSMC 40LP
  • Library of LVDS IOs cells for TSMC 65LP
    • TSMC 65 LP
    • 2.5V/1.2V IO/Core transistors
    • Fully compliant with TIA/EIA-644-A-2001
    Block Diagram -- Library of LVDS IOs cells for TSMC 65LP
  • NVM OTP XBC TSMC N7 1.8V
    • Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs
    • Synopsys’ embedded one-time programmable (OTP) non-volatile memory (NVM) IP, based on XHF architecture, enables designers to address these challenges
    • Synopsys’ OTP NVM IP architecture provides high levels of security, high yields, low power, and excellent reliability, which is why Synopsys OTP NVM is the leader in antifuse technology with >10B units shipped and availability in more than a dozen foundries
    • Synopsys OTP NVM IP is silicon-verified in TSMC N4P, N5, N5A, N6, and N7
    Block Diagram -- NVM OTP XBC TSMC N7 1.8V
  • NVM OTP XBC TSMC N6 1.8V
    • Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs
    • Synopsys’ embedded one-time programmable (OTP) non-volatile memory (NVM) IP, based on XHF architecture, enables designers to address these challenges
    • Synopsys’ OTP NVM IP architecture provides high levels of security, high yields, low power, and excellent reliability, which is why Synopsys OTP NVM is the leader in antifuse technology with >10B units shipped and availability in more than a dozen foundries
    • Synopsys OTP NVM IP is silicon-verified in TSMC N4P, N5, N5A, N6, and N7
    Block Diagram -- NVM OTP XBC TSMC N6 1.8V
  • NVM OTP XBC TSMC N5A 1.2V Automotive Grade 1 with Functional Safety
    • Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs
    • Synopsys’ embedded one-time programmable (OTP) non-volatile memory (NVM) IP, based on XHF architecture, enables designers to address these challenges
    • Synopsys’ OTP NVM IP architecture provides high levels of security, high yields, low power, and excellent reliability, which is why Synopsys OTP NVM is the leader in antifuse technology with >10B units shipped and availability in more than a dozen foundries
    • Synopsys OTP NVM IP is silicon-verified in TSMC N4P, N5, N5A, N6, and N7
    Block Diagram -- NVM OTP XBC TSMC N5A 1.2V Automotive Grade 1 with Functional Safety
  • NVM OTP XBC TSMC N5 1.2V
    • Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs
    • Synopsys’ embedded one-time programmable (OTP) non-volatile memory (NVM) IP, based on XHF architecture, enables designers to address these challenges
    • Synopsys’ OTP NVM IP architecture provides high levels of security, high yields, low power, and excellent reliability, which is why Synopsys OTP NVM is the leader in antifuse technology with >10B units shipped and availability in more than a dozen foundries
    • Synopsys OTP NVM IP is silicon-verified in TSMC N4P, N5, N5A, N6, and N7
    Block Diagram -- NVM OTP XBC TSMC N5 1.2V
  • NVM OTP XBC TSMC N4P 1.2V
    • Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs
    • Synopsys’ embedded one-time programmable (OTP) non-volatile memory (NVM) IP, based on XHF architecture, enables designers to address these challenges
    • Synopsys’ OTP NVM IP architecture provides high levels of security, high yields, low power, and excellent reliability, which is why Synopsys OTP NVM is the leader in antifuse technology with >10B units shipped and availability in more than a dozen foundries
    • Synopsys OTP NVM IP is silicon-verified in TSMC N4P, N5, N5A, N6, and N7
    Block Diagram -- NVM OTP XBC TSMC N4P 1.2V
  • Embedded flash IP, 1.8V/5V TSMC 180nmBCD
    • Supports high temperature and long retention life time for severe automotive requirement
    • Low power in Program/Erase operation for power critical applications
    • Requires few (2~3) additional masks
    • No change to SPICE model of Standard CMOS process, for re-using existing design and IP
    Block Diagram -- Embedded flash IP, 1.8V/5V TSMC 180nmBCD
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