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Memory & Libraries IP

Welcome to the ultimate Memory & Libraries IP hub! Explore our vast directory of Memory & Libraries IP.

Memory & Libraries IP cores include a large listing of memory compilers, non-volatile memory (NVM), logic libraries, and IO solutions.

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Search (4,351)
Compare 4,351 Memory & Libraries IP from 92 vendors (1 - 10)
  • ReRAM NVM in SkyWater 130nm
    • Technology: 130nm, SkyWater S130
    • Mask Adder: 2
    • Supply Voltage: 1.8V Read, 1.8V+3.3/3.6V Program
    • Read Access Time: <20nsec
    • Operation Temp.: -40°C - 125°C (can be extended to -55°C)
    • Capacity: 256 Kbit (can be customized for 128Kbit - 2Mbit)
    • Data Bus Width (Read): 32-bit (can be customized to 16-bit to 128-bit)
    Block Diagram -- ReRAM NVM in SkyWater 130nm
  • IO Library - GLOBALFOUNDRIES 22FDX
    • Library contains approx. 60 IO cells
    • Support for all metal-stacks of 22FDX®
    • Low voltage cells with nominal core voltages down to 0.4 V for glue-less interfacing to ULV Racyics® ABX digital standard cell domains
    • Low leakage cells for ultra low power always-on domain usage
    Block Diagram -- IO Library - GLOBALFOUNDRIES 22FDX
  • Single Rail SRAM GLOBALFOUNDRIES 22FDX
    • Ultra-low voltage logic designs using adaptive body biasing demand dense SRAM solutions which fully integrate in the ABB aware implementation and sign-off flow of the Racyics® ABX Platform solution.
    • The Racyics® Single Rail SRAM supports ultra-low voltage operation down to 0.55 V where logic designs with Minimum-Energy-Point are implemented.
    Block Diagram -- Single Rail SRAM GLOBALFOUNDRIES 22FDX
  • Dual-Rail SRAM Globalfoundries 22FDX
    • Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
    • Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABB
    Block Diagram -- Dual-Rail SRAM Globalfoundries 22FDX
  • Standard Cell Libraries - GLOBALFOUNDRIES 22FDX
    • Body biasing is a disruptive 22FDX® feature which enables the adaption of transistor threshold voltages after production during device operation.
    • Racyics® dense 9T logic standard cells libraries and low power 8T standard cell libraries are fully enabled for the adaptive body biasingaware implementation and sign-off flow of the Racyics® ABX® Platform solution.
    Block Diagram -- Standard Cell Libraries - GLOBALFOUNDRIES 22FDX
  • Embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability
    • SuperFlash technology
    • CMOS compatible
    • Up to 500K cycle endurance
    Block Diagram -- Embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability
  • 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
    • A Flipchip I/O Library with dynamitcally switchable 1.8V/3.3V GPIO, 5V I2C/SM- Bus ODIO, 5V OTP Cell, 1.8V & 3.3V Analog Cells and associated ESD.
    • A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
    Block Diagram -- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
  • 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
    • A 1.8V/3.3V flip-chip I/O library with 4kV HBM ESD protection, I2C compliant ODIO and Hot-Plug Detect.
    • This library is a production-quality, silicon-proven I/O library in TSMC 16nm technology.
    • Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level.
    Block Diagram -- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
  • 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
    • A 1.8V/3.3V flip-chip I/O library with 4kV HBM ESD protection, I2C compliant ODIO and Hot-Plug Detect.
    • This library is a production-quality, silicon-proven I/O library in TSMC 12nm technology.
    • Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level.
    Block Diagram -- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
  • 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
    • A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V to 5V GPIO, 1.8V to 5V analog, with ultra low-cap/low-leakage RF solutions.
    • This silicon proven flip-chip compatible library in TSMC 180nm BCD features a multi-voltage GPIO, 1.8V to 5V analog I/O, and ultra-low capacitance and low leakage 36V+ ESD solutions. The library also includes 5V RF pads.
    Block Diagram -- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
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