Memory & Libraries IP

This ESD library is a silicon-proven set of discrete, pad-independent ESD clamps for GlobalFoundries 28nm technology.
The library is designed to provide robust ESD protection for power domains and low-speed signals in advanced SoCs where traditional pad-based protection is insufficient or impractical.

A SkyWater I/O Library combining standard GPIO, I2C-compatible ODIO, analog I/O, and integrated LVDS for robust mixed-signal and moderate-speed differ ential interfaces.

Advanced Security: Encrypted storage in OTP using dynamic root key from SRAM PUF
System-Level Security Extension: Add-on allows sharing the SRAM PUF to protect chip-level assets
Flexible Security Configuration: Secure regions within OTP can be tailored to meet specific needs

Ultra-Low Leakage - GLOBALFOUNDRIES low-leakage 6T L110 bit cells with High Vt and low leakage periphery to ensure minimal leakage and high yield.
Multi-Bank Architecture - Memory split into 1 to 4 banks for reduced bit line length and enhanced timing.
Ultra Low Power Standby - Built-in source biasing trims standby current to a minimum for data retention.

Uses 8T-TP185SL bit cells.
Isolated Supplies: Periphery and array power domains can be independently powered down in standby mode.
Deep Sleep Standby Mode: Memory retains data at minimal power via internal biasing.

Ultra-Low Leakage: High VT (HVT) are used to minimize leakage performance.
Bit Cell: Utilizes Foundry’s 6T bit cells to ensure high manufacturing yields
Deep Sleep Mode Retains data a minimal power consumption. Dedicated standby mode reduces power required to an absolute minimum to retain the memory contents.

Ultra low power data retention. Memory instances generated by the Bulk 22ULL go into a deep sleep mode that retains data at minimal power consumption.
Self biasing. The SP SRAM 22ULL internal self-biasing capabilities provide ease of IP integration.
High yield. To ensure high manufacturing yield, bulk 22ULL uses low leakage 6T (0.110µ2) bit cells and is consistent with Design for Manufacturing (DFM) guidelines for the Bulk 22ULL process.
High usability. All signal and power pins are available on metal 4 while maintaining routing porosity in metal 4. Power pins can optionally be made available on metal 5 to simplify the power connections at the chip level.

Ultra-Low Leakage: High VT (HVT) are used to minimize leakage performance
Bit Cell: Utilizes Low Leakage 6T bit cells to ensure high manufacturing yields
Ultra Low Power Standby: Internally generated bias voltage for low leakage data retention
Isolated Array and Periphery supplies: Periphery voltage can be shut off to further reduce standby power

Ultra-Low Leakage: High VT (HVT) are used to minimize leakage performance
Bit Cell: Utilizes Low Leakage 6T bit cells to ensure high manufacturing yields
Ultra Low Power Standby: Internally generated bias voltage for low leakage data retention