Memory & Libraries IP

The SLM High-Speed Access and Test (HSAT) IP combined with the TestMAX® ALE software uses standard high speed IO interfaces such as PCIe and USB, to get test, debug and monitoring data in and out of an SoC at Gigabit data rates and avoids the need for large numbers of test and interface pins.
Test time can be reduced because the link between the test time and GPIO data rate is eliminated. Further, this solution provides a key component for Synopsys Silicon Lifecycle Management solution allowing manufacturing tests to be repeated in-system and in-field as well as providing high speed access to PVT and functional monitor dat

The SD 3.0 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead.

A 1.0V to 5V Analog I/O library that includes an HDMI, LVDS, and Analog/RF Low Capacitance pad set in TSMC 45/40nm HPM process.
This library is collection of analog only IO and Power/Ground pads that include ESD. The target applications are high performance analog interfaces including HDMI, RF, LVDS, basic analog and other applications.
The pads include a host of specialty features including fail safe, low capacitance, high ESD protection, and IEC robustness.

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
It includes an optional digi logic circuitry which is required for high-speed operations
It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
It includes an optional digi logic circuitry which is required for high-speed operations
It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
It includes an optional digi logic circuitry which is required for high-speed operations
It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
It includes an optional digi logic circuitry which is required for high-speed operations
It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
It includes an optional digi logic circuitry which is required for high-speed operations
It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
It includes an optional digi logic circuitry which is required for high-speed operations
It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
It includes an optional digi logic circuitry which is required for high-speed operations
It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards