Memory & Libraries IP

Compare 4,117 Memory & Libraries IP from 83 vendors (1 - 10)

ReRAM NVM in DB HiTek 130nm BCD
- 10K cycles endurance
- >10 years retention at 125°C
- Ultra-low power consumption
- Low-cost NVM – requires only two additional masks
ReRAM NVM in SkyWater 130nm
- Weebit Resistive RAM (ReRAM) is a new type of Non-Volatile Memory (NVM) that is designed to be the successor to flash memory.
- Weebit ReRAM IP can provide a high level of differentiation for System-on-Chip (SoC) designs, with performance, power, cost, security, environmental, and a range of additional advantages compared to flash and other NVMs.
- Weebit’s first ReRAM IP product is available now in SkyWater Technology’s 130nm CMOS process (S130). The technology is fully qualified, available for integration in SkyWater’s users’ SoCs, and ready for production.
MRAM Synthesizable Transactor
- Supports all the MRAM commands as per the MR2A16A and MR0A08B specifications.
- Supports Symmetrical high-speed read and write with fast access time.
- Supports SRAM Compatible timing
- Supports native non-volatility
Stand-Alone ESD Cell in GF 28nm
- This ESD library is a silicon-proven set of discrete, pad-independent ESD clamps for GlobalFoundries 28nm technology.
- The library is designed to provide robust ESD protection for power domains and low-speed signals in advanced SoCs where traditional pad-based protection is insufficient or impractical.
I/O Library with LVDS in SkyWater 90nm
- A SkyWater I/O Library combining standard GPIO, I2C-compatible ODIO, analog I/O, and integrated LVDS for robust mixed-signal and moderate-speed differ ential interfaces.
Secure Storage Solution for OTP IP
- Advanced Security: Encrypted storage in OTP using dynamic root key from SRAM PUF
- System-Level Security Extension: Add-on allows sharing the SRAM PUF to protect chip-level assets
- Flexible Security Configuration: Secure regions within OTP can be tailored to meet specific needs
Single Port High-Speed Multi Bank SRAM Memory Compiler on GF 22FDX+
- Ultra-Low Leakage - GLOBALFOUNDRIES low-leakage 6T L110 bit cells with High Vt and low leakage periphery to ensure minimal leakage and high yield.
- Multi-Bank Architecture - Memory split into 1 to 4 banks for reduced bit line length and enhanced timing.
- Ultra Low Power Standby - Built-in source biasing trims standby current to a minimum for data retention.
Dual Port Register File Compiler (1 Read-only port, 1 Write-only port) - GF 22FDX+
- Uses 8T-TP185SL bit cells.
- Isolated Supplies: Periphery and array power domains can be independently powered down in standby mode.
- Deep Sleep Standby Mode: Memory retains data at minimal power via internal biasing.
High Speed Single Port Compiler on TSMC 40nm ULP
- Low voltage
- Ultra low power data retention
- Self biasing
- Soft error immunity
Single Port Register File Compiler on N22ULL
- Ultra-Low Leakage: High VT (HVT) are used to minimize leakage performance.
- Bit Cell: Utilizes Foundry’s 6T bit cells to ensure high manufacturing yields
- Deep Sleep Mode Retains data a minimal power consumption. Dedicated standby mode reduces power required to an absolute minimum to retain the memory contents.

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