Memory & Libraries IP

Welcome to the ultimate Memory & Libraries IP hub! Explore our vast directory of Memory & Libraries IP.

Memory & Libraries IP cores include a large listing of memory compilers, non-volatile memory (NVM), logic libraries, and IO solutions.

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Compare 4,315 Memory & Libraries IP from 89 vendors (1 - 10)
  • LVDS Deserializer IP
    • The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
    • Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.
    Block Diagram -- LVDS Deserializer IP
  • LVDS Serializer IP
    • The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels.
    • The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components.
    Block Diagram -- LVDS Serializer IP
  • MIPI D-PHY/LVDS Combo Receiver IP
    • The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard.
    • The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI).
    Block Diagram -- MIPI D-PHY/LVDS Combo Receiver IP
  • MIPI D-PHY/LVDS Combo Transmitter IP
    • The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY and a high performance 4-channel LVDS Serializer implemented using digital CMOS technology.
    • In LVDS mode, both the serial and parallel data are organized into 4 channels. The parallel data is 7 bits wide per channel. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
    Block Diagram -- MIPI D-PHY/LVDS Combo Transmitter IP
  • ReRAM NVM in SkyWater 130nm
    • Technology: 130nm, SkyWater S130
    • Mask Adder: 2
    • Supply Voltage: 1.8V Read, 1.8V+3.3/3.6V Program
    • Read Access Time: <20nsec
    • Operation Temp.: -40°C - 125°C (can be extended to -55°C)
    • Capacity: 256 Kbit (can be customized for 128Kbit - 2Mbit)
    • Data Bus Width (Read): 32-bit (can be customized to 16-bit to 128-bit)
    Block Diagram -- ReRAM NVM in SkyWater 130nm
  • IO Library - GLOBALFOUNDRIES 22FDX
    • Library contains approx. 60 IO cells
    • Support for all metal-stacks of 22FDX®
    • Low voltage cells with nominal core voltages down to 0.4 V for glue-less interfacing to ULV Racyics® ABX digital standard cell domains
    • Low leakage cells for ultra low power always-on domain usage
    Block Diagram -- IO Library - GLOBALFOUNDRIES 22FDX
  • Single Rail SRAM GLOBALFOUNDRIES 22FDX
    • Ultra-low voltage logic designs using adaptive body biasing demand dense SRAM solutions which fully integrate in the ABB aware implementation and sign-off flow of the Racyics® ABX Platform solution.
    • The Racyics® Single Rail SRAM supports ultra-low voltage operation down to 0.55 V where logic designs with Minimum-Energy-Point are implemented.
    Block Diagram -- Single Rail SRAM GLOBALFOUNDRIES 22FDX
  • Dual-Rail SRAM Globalfoundries 22FDX
    • Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
    • Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABB
    Block Diagram -- Dual-Rail SRAM Globalfoundries 22FDX
  • Standard Cell Libraries - GLOBALFOUNDRIES 22FDX
    • Body biasing is a disruptive 22FDX® feature which enables the adaption of transistor threshold voltages after production during device operation.
    • Racyics® dense 9T logic standard cells libraries and low power 8T standard cell libraries are fully enabled for the adaptive body biasingaware implementation and sign-off flow of the Racyics® ABX® Platform solution.
    Block Diagram -- Standard Cell Libraries - GLOBALFOUNDRIES 22FDX
  • Embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability
    • SuperFlash technology
    • CMOS compatible
    • Up to 500K cycle endurance
    Block Diagram -- Embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability
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