Receiver/Transmitter IP
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Receiver/Transmitter IP
from 35 vendors
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LVDS Deserializer IP
- The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
- Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.
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10/100 Mbit Ethernet MAC
- The GRETH core implements a 10/100 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface.
- The core implements the 802.3-2002 Ethernet standard. Receive and transmit data is autonomously transferred between the Ethernet MAC and the AMBA AHB bus using DMA transfers.
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SpaceWire link controller with SpaceWire RMAP support and AMBA host interface
- Full implementation of Spacewire standard
- Protocol ID extension ECSS-E-50-12 part 2
- Optional RMAP protocol draft C
- AMBA AHB back-end with DMA
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UART
- Functionally compatible with 16550.
- Supports Character (16450) and FIFO (16550) mode operations.
- Designed optimized for ASIC and PLD implementations.
- Synchronous design with edge triggered flip-flops based on system clock input.
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Universal Asynchronous Receiver/Transmitter Module
- The UARTmodule is part of Inicore's IPmodule family. Universal asynchronous receiver and transmitter, using the RS232 protocol, are often used to connect peripheral devices to a central controller.
- The UARTmodule has one receive and one transmit channel, receive and transmit buffers, an interrupt controller as well as a local bus interface.
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Serial Peripheral Interface (SPI) Master Module
- The SPIMmodule is part of Inicore's IPmodule family. The serial peripheral interface (SPI) protocol is often used to connect peripheral devices to a CPU.
- Several slave devices can be connected to the same bus. Since it is a serial bus, the pin count is low.
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UART eVC
- UART eVC is a fully documented, off the shelf component for Cadence Specman Elite functional verification environment. At the heart of every asynchronous serial system is the Universal Asynchronous Receiver/Transmitter (UART).
- The UART is responsible for implementing the asynchronous communication process as both a transmitter and a receiver (both encoding and decoding data frames). The UART not only controls the transfer of data, but the speed at which communication takes place.
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8530 - Serial Communication Controller
- Product Features
- Synchronous / Isosynchronous data rates
- Asynchronous capabilities
- Synchronous capabilities
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UART - Universal Asynchronous Receiver / Transmitter Core
- The SI40U550 IP core is a Universal Asynchronous Receiver Transmitter fully compatible with the de - facto standard 16550 UART.
- The SI40U550 core performs serial - to - parallel conversions on data received from a peripheral device or modem and parallel - to - serial conversion on data received from the host. The host can read the UART status at any time.
- The SI40U550 core includes complete modem control capability and a processor interrupt system that can be tailored to minimize software management of the communications link.
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SDI II Intel® FPGA IP Core
- The serial digital interface (SDI) II Intel FPGA intellectual property (IP) core implements a transmitter, receiver or full-duplex SDI at standard definition, high definition or 3G to 12G rate as defined by the Society of Motion Picture and Television Engineers
- The SDI II IP core supports multiple standards
- These modes provide automatic receiver rate detection and transceiver dynamic reconfiguration.