Receiver/Transmitter IP

The GRETH core implements a 10/100 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface.
The core implements the 802.3-2002 Ethernet standard. Receive and transmit data is autonomously transferred between the Ethernet MAC and the AMBA AHB bus using DMA transfers.

GRSCRUB is an FPGA supervisor responsible for programming and scrubbing the FPGA configuration memory to prevent the accumulation of radiation-induced errors.
The GRSCRUB IP currently supports the AMD/Xilinx Kintex UltraScale and Virtex-5 FPGA families.

The UARTmodule is part of Inicore's IPmodule family. Universal asynchronous receiver and transmitter, using the RS232 protocol, are often used to connect peripheral devices to a central controller.
The UARTmodule has one receive and one transmit channel, receive and transmit buffers, an interrupt controller as well as a local bus interface.

The SPIMmodule is part of Inicore's IPmodule family. The serial peripheral interface (SPI) protocol is often used to connect peripheral devices to a CPU.
Several slave devices can be connected to the same bus. Since it is a serial bus, the pin count is low.

The SI40U550 IP core is a Universal Asynchronous Receiver Transmitter fully compatible with the de - facto standard 16550 UART.
The SI40U550 core performs serial - to - parallel conversions on data received from a peripheral device or modem and parallel - to - serial conversion on data received from the host. The host can read the UART status at any time.
The SI40U550 core includes complete modem control capability and a processor interrupt system that can be tailored to minimize software management of the communications link.

Run-time programmable Master or slave mode operation.
Bit rates generated in Master mode: ÷2, ÷4, ÷6, ÷8, ÷10, ÷12, ...÷512 of the system clock.
Bit rates supported in Slave mode: fSCK ≤ fSYSCLK ÷4
Support for 1,2,4 or unlimitted bytes multi-byte frame data transfers, run-time programmable.