Receiver/Transmitter IP

The Universal Asynchronous Receiver/Transmitter (UART) is a hardware device that translates data between parallel and serial forms.
UARTs are commonly used in conjunction with communication standards such as TIA (formerly EIA) RS-232, RS-422 or RS-485.

This is a complete implementation of a 16550 UART.
The UART contains the following main sections: Configuration Registers, Baud Rate, Generator, Transmitter, Receiver, Interrupt Generation Logic, Modem Control Logic

Run-time programmable Master or slave mode operation.
Bit rates generated in Master mode: ÷2, ÷4, ÷6, ÷8, ÷10, ÷12, ...÷512 of the system clock.
Bit rates supported in Slave mode: fSCK ≤ fSYSCLK ÷4
Support for 1,2,4 or unlimitted bytes multi-byte frame data transfers, run-time programmable.

The UART Verification IP provides a comprehensive solution for validating UART communication interfaces in System-on-Chip (SoC) designs. It simulates both transmission and reception functionality to ensure data integrity. This IP supports error injection, debugging tools, and protocol compliance checking. It is ideal for ensuring reliability and protocol compliance in UART-based peripherals used in various applications, from simple devices to advanced systems.

Capable of running all existing 16450 and 16550a software
Fully Synchronous design. All inputs and outputs are based on the rising edge of clock
In FIFO mode, transmitter and receiver are each buffered with up to 256 byte FIFO’s to reduce the number of interrupts presented to the CPU
Available with FIFO sizes of 8, 16, 32, 64, 128 or 256 bytes

Capable of running all existing 16450 and 16550a software
Fully Synchronous design. All inputs and outputs are based on rising edge of clock
In FIFO mode, the transmitter and receiver are each buffered with 16 byte FIFOs to reduce the number of interrupts presented to the CPU
Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data

Capable of running all existing 16450 software
Fully Synchronous design. All inputs and outputs are based on the rising edge of clock
Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
Independently controlled transmit, receive, line status and data set interrupts

Fully compatible with ds8251.
Transmit and receive commands allow the user to transmit and receive USART data.
Configurable Baud rate.
Programmable word length, stop bits, and parity