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Disk Controller IP

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Compare 8 Disk Controller IP from 5 vendors (1 - 8)
  • SAS Initiator, 12G, 4 Ports, 48 Gbps
    • The SAS Initiator Controller IP Core provides an interface to high-speed serial link replacement for the parallel SCSI attachment of mass storage devices.
    • Maximum supported bandwidth is 48 Gbps. The serial link employs multiple high-speed gigabit transceivers.
    Block Diagram -- SAS Initiator, 12G, 4 Ports, 48 Gbps
  • Serial ATA I/II Device Controller IP Core
    • The Serial ATA Device Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices.
    • The serial link employed is a high-speed differential layer that utilizes Gigabit technology and 8b/10b encoding.
    Block Diagram -- Serial ATA I/II Device Controller IP Core
  • ATA-7 (UDMA 133) Host controller
    • PIO modes 0-4
    • Multi-word DMA modes 0-2
    • Ultra DMA modes 0-6
    • Programmable timings for PIO and DMA modes
    • Support for Ultra DMA pause and termination
    • Standard slave Wishbone interface to
    Block Diagram -- ATA-7 (UDMA 133) Host controller
  • ATA-7 (UDMA 133) Target Interface
    • PIO modes 0-4
    • IORDY signaling for PIO cycle extension
    • Multi-word DMA modes 0-2
    • Ultra DMA modes 0-6
    Block Diagram -- ATA-7 (UDMA 133) Target Interface
  • Real Time Clock
    • The RTC (Real Time Clock) provides an automatic wake-up to manage all low-power modes.
    • It is an independent timer. The RTC provides a set of continuously running counters which can be used, with suitable software, to provide a clockcalendar function.
  • SATA Host Controller
    • SATA Spec Rev2.6 compatible Link and Transport layer
    • Supports 1.5Gbps and 3Gbps data rates
    • Compliant to AHCI 1.1, support one port
    • Supports Native Command Queuing (FPDMA)
  • Run Time Phase Alignment Circuit
    • 1. Sync Clock Generation in one clock duation.
    • 2. Generatted clock is Phase Aligned with the incoming data. Data can be received.
    • 3. Tx and Rx Clock can be up to +/-5% off of the frequency range. This block can accomode and can generate same tx freq at the rx side.
    • 4. This Rx Clock can be used to -
  • Bit Block Transfer 2D video accelerator
    • Supported 16 different ROP2 operations
    • Contiguous and Array image addressing modes
    • Color keyed transparency
    • Color Expansion for Font acceleration
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Semiconductor IP