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898
Standard cell IP
from 15 vendors
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10)
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256-steps adjustable delay cell
- Process: UMC 40nm Logic and Mixed-Mode 2.5V/1.1V Low Power Process
- Adjustable 8-bit delay steps, Maximum delay time 25.5ns, and Minimum delay time = 0.1ns (resolution: 0.1ns).
- Power Supply: Core power supply 1.1V
- Area : 600um ^2
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Standard Cell Libraries - GLOBALFOUNDRIES 22FDX
- Contains >300 cells, various Vt and channel length options
- Robust power supply rails on M2, optimized M1 pin access with at least two on-track M2 access points
- DFM and variability optimized layouts and variation aware placement attributes for automated place&route
- Enabled for reliable ULV operation down to 0.4 V in combination with adaptive forward body bias
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CLICK - The universal solution of power gating for the whole SoC
- Make the integration easier thanks to ringstyle
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CLICK - The universal solution of power gating for the whole SoC
- Make the integration easier thanks to ringstyle
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CLICK - The universal solution of power gating for the whole SoC
- - Fully automated island kit generator
- - Automatic digital power switch controller TRC, single or distributed
- - Scripts for easier and faster implementation
- - Close or open ring implementation