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Standard cell IP

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Compare 900 Standard cell IP from 16 vendors (1 - 10)
  • Standard Cell Libraries - GLOBALFOUNDRIES 22FDX
    • Body biasing is a disruptive 22FDX® feature which enables the adaption of transistor threshold voltages after production during device operation.
    • Racyics® dense 9T logic standard cells libraries and low power 8T standard cell libraries are fully enabled for the adaptive body biasingaware implementation and sign-off flow of the Racyics® ABX® Platform solution.
    Block Diagram -- Standard Cell Libraries - GLOBALFOUNDRIES 22FDX
  • 1.5V to 3.3V GPIO with Tri-State Output Driver in GF 180nm
    • A GlobalFoundries 180nm BCD Lite Wirebond GPIO library with tri-state out- put driver, schmitt trigger receiver and associated ESD.
    • This silicon-proven, wirebond library in GlobalFoundries 180nm BCD lite is a specialty I/O similar to Soundwire.
    • Featuring a 1.5V to 3.3V GPIO, as well as a tri-state output driver, an analog test point switch, and 7V OTP mode.
    Block Diagram -- 1.5V to 3.3V GPIO with Tri-State Output Driver in GF 180nm
  • 256-steps adjustable delay cell
    • Process: UMC 40nm Logic and Mixed-Mode 2.5V/1.1V Low Power Process
    • Adjustable 8-bit delay steps, Maximum delay time 25.5ns, and Minimum delay time = 0.1ns (resolution: 0.1ns).
    • Power Supply: Core power supply 1.1V
    • Area : 600um ^2
    Block Diagram -- 256-steps adjustable delay cell
  • Standard Cell Libraries
    • High Performance Library Variant
    • Low Power Library Variant
  • Standard Cell Library
    • Basic Cells: A full suite of fundamental logic gates and flip-flops.
    • Optimal Cells: High-performance variants of basic cells, optimized for power, area, and speed, including high-speed flip-flops, advanced multiplexers, clock gated cells, clock buffers, arithmetic cells and custom-designed cells for critical paths.
  • Standard Cell Libraries GF 55nm
    • The Standard Cell libraries deliver thousands of highly optimized cells with each one being optimized for power, area, speed, routing, and yield.
    • These libraries may be extended with Power Management Kits, taking power reduction to the next level, and ECO Kits to enable late-stage design modifications.
  • Standard Cell Library, Low Voltage Operation 0.45 V TSMC N3P
    • Nominal voltage of 0.75 V +/-10 %
    • Low voltage of 0.45 V +/-10 %
    • Track height: 7.5T
    • Operating temperature: -40°C to 125°C
  • CSMC 0.13um 9track LVT Standard Cell Library, 1.2v operating voltage
    • CSMC 0.13um generic process
    • Wide Variety of Cell Functions and Drive Strengths.
    • Process-Specific Optimization for High-Density and Low-Power.
    • Engineered for Synthesizability and Routability.
  • CSMC 0.13um 9track HVT Standard Cell Library, 1.2v operating voltage
    • CSMC 0.13um generic process
    • Wide Variety of Cell Functions and Drive Strengths.
    • Process-Specific Optimization for High-Density and Low-Power.
    • Engineered for Synthesizability and Routability.
  • CSMC 0.18um Standard Cell Library, 1.8v operating voltage
    • CSMC 0.18um Mix CMOS process
    • Wide Variety of Cell Functions and Drive Strengths.
    • Process-Specific Optimization for High-Density, High-Speed, and Low-Power.
    • Engineered for Synthesizability and Routability.
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