The Pulse

The Semiconductor IP Marketplace that puts you first

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Spotlight

  • Power-OK Monitor
    • The agilePOK is a Power OK monitor that consists of a voltage reference and comparators to set a programmable high and low threshold level for power supply integrity detection.
    • The number of trigger outputs can be customized and each threshold can be adjusted during operation to support DVFS operation.
    • This monitor can be used to detect loss of power or attacks to the power supply.
    Block Diagram -- Power-OK Monitor
  • RISC-V-Based, Open Source AI Accelerator for the Edge
    • Coral NPU is a machine learning (ML) accelerator core designed for energy-efficient AI at the edge.
    • Based on the open hardware RISC-V ISA, it is available as validated open source IP, for commercial silicon integration.
    Block Diagram -- RISC-V-Based, Open Source AI Accelerator for the Edge
  • Securyzr™ neo Core Platform
    • Securyzr™ neo Core Platform is Secure-IC’s enhanced version of its flagship offering Securyzr™ integrated Secure Element (iSE) Series.
    • Thanks to its common platform, the entire Securyzr™ neo Series is now faster and more optimized than ever.
    • With an optimal Power Performance Area (PPA), Secure-IC is offering a more comprehensive and mature solution to address all security needs from the different applications: spanning from IoT, Factory Automation, AIoT, Automotive, Cloud & Datacenter, to Mobile.
    Block Diagram -- Securyzr™ neo Core Platform
  • 112G Multi-SerDes
    • Designed with a small footprint, ultra-low latency, and low power consumption, the 112G SerDes maximizes bidirectional memory access efficiency, reduces software complexity, and helps chip developers leverage existing Ethernet infrastructure to significantly lower Total Cost of Ownership (TCO).
    • Featuring IEEE 802.3-compliant Forward Error Correction (FEC), 35dB ultra-high channel loss compensation, and adaptive high-speed equalization technologies (CTLE, FFE), it provides full-cycle link protection—from error correction to pre-warning—enabling highly compatible, stable, and efficient chip-to-chip connectivity solutions.
    Block Diagram -- 112G Multi-SerDes
  • SHA3 Cryptographic Hash Cores
    • Completely self-contained; does not require external memory
    • SHA3-224, SHA3-256, SHA3-384, and SHA3-512 support SHA-3 algorithms per FIPS 202.
    • SHAKE128 / SHAKE256 XOF support is included.
    • Flow-through design; flexible data bus width
    Block Diagram -- SHA3 Cryptographic Hash Cores
  • ISO/IEC 7816 Verification IP
    • The ISO/IEC 7816 Verification IP offers a streamlined and efficient solution for verifying System-on-Chip (SoC) and IP designs that incorporate contactless communication.
    • The ISO/IEC 7816 VIP is compliant with ISO/IEC 7816 Specifications. This VIP is light weight with easy plug-and- play interface so that there is no hit on the design cycle time.
    Block Diagram -- ISO/IEC 7816 Verification IP
  • UCIe Die-to-Die Chiplet Controller
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    Block Diagram -- UCIe PHY & D2D Adapter
  • TSMC CLN5FF GUCIe LP Die-to-Die PHY
    Block Diagram -- TSMC CLN5FF GUCIe LP Die-to-Die PHY
  • PCIe 7.0 Controller with AXI
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
  • PCIe 7.0 PHY in TSMC (N5, N3P)
  • RISC-V CPU IP
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar
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