The Semiconductor IP Marketplace

Try an example: PCIe 7.0
☰ Semiconductor IP

The Pulse

The Semiconductor IP Marketplace that puts you first

Semi IP Hub's mission is to provide you with a platform where you can find Silicon IP cores for your next project without being harassed by dozens of sellers.

Here, your contact details are not shared with third parties unless you request to be contacted by a supplier.

Spotlight

  • 1.6T/3.2T Multi-Channel MACsec Engine with TDM Interface (MACsec-IP-364)
    • The MACsec-IP-364 is a MACsec/IPsec engine developed specifically for high-speed, multi-rate and multi-port Ethernet devices.
    • Its architecture provides an optimal multi-protocol solution for aggregate throughput for 1.6T and 3.2T.
    • The MACsec-IP-364 is ideal for deployment in data center, enterprise and carrier network applications, as well as network-attached high-performance computing.
    Block Diagram -- 1.6T/3.2T Multi-Channel MACsec Engine with TDM Interface (MACsec-IP-364)
  • 100G MAC and PCS core
    • KMX 100G MAC and PCS core, which consists of media access control (MAC) module, physical coding sublayer (PCS) module and physical medium attachment (PMA) module, is compliant with the IEEE 802.3ba-2010 standard.
    • The core implements RS FEC as defined in IEEE 802.3bj Clause 91 with independent bit error detection and bit error correction.
    Block Diagram -- 100G MAC and PCS core
  • xSPI + eMMC Combo PHY IP
    • This IP integrates both xSPI (Expanded Serial Peripheral Interface) and eMMC 5.1 PHY (Physical Layer) into a single unified solution, enabling support for two distinct memory protocols within the same IP.
    • By combining the PHY layers for both interfaces, the design simplifies system integration, reduces area and pin count, and enhances design flexibility for SoCs that require both boot and high-speed storage functionality.
    Block Diagram -- xSPI + eMMC Combo PHY IP
  • NavIC LDPC Decoder
    • Throughput matching the required specifications.
    • Bit-Error-Rate (BER) and Block-Error-Rate (BLER) performance meet the required specifications.
    • Compliant with 'ISRO-NAVIC-ICD-SPS-L1-1.0' standard
  • Complex Digital Up Converter
    • High-precision 16-bit complex digital up-converter / IQ modulator (DUC) with a fully configurable interpolation filter stage.
    • Ideal for the conversion of baseband signals to IF.
    • Features a precision digital oscillator (DDS) and an optimized interpolation filter section.
       
  • Bluetooth Low Energy 6.0 Digital IP
    • The SB1001-CM BLE 6.0 digital modem and baseband controller IP enables industry-leading, ultra-efficient, wireless SoCs for multiple connected applications.
    • Industry leading modem link budget for RF environment reliability and resilience, industry leading support for scalable numbers of connections and a Zephyr driver for ease of host integration

UCIe Controller IP View All

  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • UCIe Die-to-Die PHY
    • High Bandwidth Density and Data Rates
    • Package Configurability
    • Energy Efficiency
    • Fully Integrated Solution
    Block Diagram -- UCIe Die-to-Die PHY

PCIe 7.0 IP View All

  • PCIe 7.0 Controller with AXI
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Separate native TX/RX data path separating posted/Non posted/completion traffic
    • Handles up to 4 TLPs per cycle
    • Advanced PIPE modes and port bifurcation
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
  • PCIe 7.0 PHY in TSMC (N5, N3P)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SSC)

AI IP View All

  • RISC-V CPU IP
    • RISC-V RVA23 Compliant 
    • >18 SPECint2006/GHz
    • 8-wide decode unit
    • Advanced branch predictor
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
    • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
    • Future proof architecture that supports the most advanced ML data types and operators
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    • RISC-V-based AI IP development for enhanced training and inference.
    • Silicon-proven solutions tailored for AI workload optimization.
    • Energy-efficient performance with industry-leading Perf/W.
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar

MIPI IP View All

RISC-V IP View All

×
Semiconductor IP