The Semiconductor IP Marketplace

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The Semiconductor IP Marketplace that puts you first

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Spotlight

  • HBM4 Controller IP
    • Supports JEDEC standard HB4 DRAM
    • DFI 5.1 compliant interface to HBM4 PHY
    • Multiport Arm® AMBA® interface (AXI™) with managed QoS per pseudo-channel or single-port host interface(HIF), per channel 
    • Data rate support 12 Gbps or higher
  • IPSEC AES-256-GCM (Standalone IPsec)
    • XIP7213E implements the Internet Protocol Security (IPsec) as standardised in RFC4303 and RFC4305.
    • The IPsec protocol defines a security infrastrucure for Layer 3 (as per the OSI model) traffic by assuring that a received packet has been sent by the transmitting station that claimed to send it.
    Block Diagram -- IPSEC AES-256-GCM (Standalone IPsec)
  • Functional-Safety & Secure LPDDR3 Memory Subsystem
    • Safe & Secure-LPDDR3 that is ready for ASIL (Automotive Safety Integrity Level) and secure by design
    • Functional Safety out-of-the box design, with an extensive ASIL documentation package.
    • Integrated security features into the controller. Characterized for extended operating conditions and long-term reliability.
  • Parameterizable compact BCH codec
    • Highly parameterizable
    • Very low area (in the largest, n = 511 t = 16 configuration, the core uses just 17K gates in ASIC)
    • Entirely self-contained (no external RAM required)
    Block Diagram -- Parameterizable compact BCH codec
  • eFPGA IP — Flexible Reconfigurable Logic Acceleration Core
    • RapidFlex eFPGA IP provides a reconfigurable, upgradeable, and iterative logic computing layer for SoCs, MCUs, AI accelerators, industrial control, and communication chips.
    • Based on RapidFlex's self-developed ArkAngel® toolchain (AAEE), our eFPGA core delivers full-flow capabilities from architecture exploration → RTL → physical implementation (GDSII) → digital design flow verification, leading the industry in performance density, integrability, and toolchain experience.
    Block Diagram -- eFPGA IP — Flexible Reconfigurable Logic Acceleration Core
  • 1G BASE-T Ethernet Verification IP
    • The 1G BASE-T Ethernet Verification IP provides deliverables an effective & efficient way to verify the components interfacing with the Ethernet interface of an IP or SoC. 
    •  The 1G Ethernet VIP is fully compliant with the IEEE standard 802.3 specification.
    • This VIP is lightweight with easy plug -and- play interface so that there is no hit on the design cycle time.
    Block Diagram -- 1G BASE-T Ethernet Verification IP

UCIe Controller IP View All

  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • TSMC CLN5FF GUCIe LP Die-to-Die PHY
    • IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
    • This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the
    Block Diagram -- TSMC CLN5FF GUCIe LP Die-to-Die PHY

PCIe 7.0 IP View All

  • PCIe 7.0 Controller with AXI
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Separate native TX/RX data path separating posted/Non posted/completion traffic
    • Handles up to 4 TLPs per cycle
    • Advanced PIPE modes and port bifurcation
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
  • PCIe 7.0 PHY in TSMC (N5, N3P)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SSC)

AI IP View All

  • RISC-V CPU IP
    • RISC-V RVA23 Compliant 
    • >18 SPECint2006/GHz
    • 8-wide decode unit
    • Advanced branch predictor
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
    • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
    • Future proof architecture that supports the most advanced ML data types and operators
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    • RISC-V-based AI IP development for enhanced training and inference.
    • Silicon-proven solutions tailored for AI workload optimization.
    • Energy-efficient performance with industry-leading Perf/W.
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar

MIPI IP View All

RISC-V IP View All

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