The Semiconductor IP Marketplace

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The Semiconductor IP Marketplace that puts you first

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Spotlight

  • Simulation VIP for Ethernet UEC
    • Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
    • Callbacks access at multiple TX and RX queue points for scoreboarding, data manipulation, and error injection
    • Transaction Tracker: Configurable tracking of all the transactions on the channels
    Block Diagram -- Simulation VIP for Ethernet UEC
  • Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
    • TSMC IP9000 Alliance member enabling automotive IP support in TSMC automotive processes
    • Automotive Documentation including Safety Manual, FMEDA and DFMEA
    • Design reliability report containing EM/IR and Aging analysis
    Block Diagram -- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
  • CAN-FD Controller
    • The Controller Area Network (CAN) is a highly reliable serial bus protocol defined in the Bosch CAN specifications for standard CAN 2.0B and CAN FD, as well as ISO 11898-1:2024.
    • The TES CAN Flexible Data-Rate Controller IP core is a Hardware IP core written in VHDL.
    Block Diagram -- CAN-FD Controller
  • Bluetooth® Low Energy 6.2 PHY IP with Channel Sounding
    • The icyTRX-LE-22 RF transceiver PHY IP delivers an optimal trade-off between power consumption and Bluetooth Low Energy (LE) RF performance — excellent sensitivity and strong interference rejection — while minimizing the overall cost for loT applications.
    • Occupying just 0.57 mm2 in a 22 nm technology (7 metal layers), the analog RF portion of the IP integrates on-chip passives and Built-In-Self-Test (BIST) structures to drive down silicon area, wafer cost, bill of materials, and production-test expenses.
    Block Diagram -- Bluetooth® Low Energy 6.2 PHY IP with Channel Sounding
  • Simulation VIP for UALink
    • The Ultra Accelerator Link (UALink) Verification IP (VIP) provides a complete bus functional model (BFM) with integrated automatic protocol checks for physical layer in addition to Media Independent Interface (MII).
    • Designed for easy integration in testbenches at IP, SoC, and system levels, the VIP helps engineers reduce time to first test, accelerate verification closure, and ensure end-product quality.
    Block Diagram -- Simulation VIP for UALink
  • General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
    • This Integer-N Hybrid (Digitally Aided Analog) PLL generates clock signals within broad frequency range.
    • Division coefficients of the embedded input and feedback dividers can be set to any integer between 1 and 64 or may be bypassed to save power.
    • Higher order dividers and/or pre-scalers are optional.
    Block Diagram -- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC

UCIe Controller IP View All

  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • TSMC CLN5FF GUCIe LP Die-to-Die PHY
    • IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
    • This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the
    Block Diagram -- TSMC CLN5FF GUCIe LP Die-to-Die PHY

PCIe 7.0 IP View All

  • PCIe 7.0 Controller with AXI
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Separate native TX/RX data path separating posted/Non posted/completion traffic
    • Handles up to 4 TLPs per cycle
    • Advanced PIPE modes and port bifurcation
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
  • PCIe 7.0 PHY in TSMC (N5, N3P)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SSC)

AI IP View All

  • RISC-V CPU IP
    • RISC-V RVA23 Compliant 
    • >18 SPECint2006/GHz
    • 8-wide decode unit
    • Advanced branch predictor
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
    • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
    • Future proof architecture that supports the most advanced ML data types and operators
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    • RISC-V-based AI IP development for enhanced training and inference.
    • Silicon-proven solutions tailored for AI workload optimization.
    • Energy-efficient performance with industry-leading Perf/W.
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar

MIPI IP View All

RISC-V IP View All

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