The Pulse
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創意電子公佈民國114 年9 月份營收報告
2025-10-07T12:07:00+00:00
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安谋科技发布CPU IP “星辰”STAR-MC3,提升传统嵌入式芯片AI处理能力及面效比
2025-09-30T13:35:00+00:00
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国产领军的全功能 GPU “风华3号” 重磅发布,多个第一赋能千行百业人工智能+
2025-09-29T11:11:00+00:00
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Allegro DVT 推出全面合规测试工具,支持 AV2 标准生态系统
2025-09-25T12:38:00+00:00
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锐成芯微推出MIPI A-PHY IP:搭建汽车电子高效数据传输网络
2025-09-25T11:43:00+00:00
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Perceptia Devices 推出 pPLL08N:紧凑型窄带射频锁相环(RF PLL)系列 IP,进一步完善 pPLL08 产品线
2025-09-25T05:00:00+00:00
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芯原推出基于FD-SOI工艺的无线IP平台,支持多样化物联网及消费电子应用
2025-09-24T05:09:00+00:00
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MIPI A-PHY达成里程碑,成为首个获全球汽车OEM采用并进入量产的SerDes标准
2025-09-23T05:40:00+00:00
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Silicon Creations在台积电FinFET工艺上完成第 1000 个项目量产流片,完整 N2 工艺 IP 库同步上线
2025-09-17T12:30:00+00:00
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Perceptia Devices 正式启动将 pPLL03 移植至三星 8 纳米工艺平台
2025-09-11T03:50:00+00:00
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新思科技领先EDA解决方案宣布拓展AI功能
2025-09-11T01:06:00+00:00
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芯測科技完成FMEDA分析 助客戶打造符合ISO 26262的車用 IC
2025-09-10T06:26:00+00:00
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熵碼科技(力旺電子子公司)與科絡達科技策略聯盟: 以PUF技術強化OTA資安防護,布局軟體定義設備時代
2025-09-09T05:53:00+00:00
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創意電子公佈民國114 年8 月份營收報告
2025-09-05T06:27:00+00:00
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IntoPIX 因开发JPEG XS 荣获 2025 艾美奖
2025-09-04T15:30:00+00:00
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让高性能计算芯片设计与CXL规范修订保持同步
2025-09-04T08:33:00+00:00
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Leader 和IntoPIX 通过JPEG XS 集成提升IP 流监控能力
2025-09-04T05:38:00+00:00
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Silicon Creations 荣获 GlobalFoundries 年度模拟混合信号 IP 合作伙伴称号
2025-09-03T14:27:00+00:00
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创意电子 (GUC) 正式加入 NVIDIA NVLink Fusion 生态系统
2025-09-03T05:42:00+00:00
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IntoPIX 和 Arkona Technologies 将下一代IP 广播工作流程的JPEG XS 密度提高一倍
2025-09-02T06:04:00+00:00
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芯来科技发布加解密IP系列与加速器IP系列产品
2025-09-01T06:47:00+00:00
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芯来助力亦芯微发布基于RISC-V的后量子密码芯片
2025-09-01T06:28:00+00:00
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格罗方德任命胡维多为中国区总裁,助力本土业务拓展
2025-09-01T06:00:00+00:00
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熵碼科技(力旺電子子公司)與科絡達科技策略聯盟: 以PUF技術強化OTA資安防護,布局軟體定義設備時代
2025-08-28T07:06:00+00:00
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Perceptia 签约 Running Springs Technology 作为中国大陆及台湾 地区代表
2025-08-27T23:40:00+00:00
The Semiconductor IP Marketplace that puts you first
Semi IP Hub's mission is to provide you with a platform where you can find Silicon IP cores for your next project without being harassed by dozens of sellers.
Here, your contact details are not shared with third parties unless you request to be contacted by a supplier.
Spotlight
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Simulation VIP for AMBA CHI-C2C
- Incorporating the latest protocol updates, the Cadence Verification IP for CHI-C2C provides a complete bus functional model (BFM), integrated automatic protocol checks, and a coverage model.
- Designed for easy integration in testbenches at IP, systems with multiple CPUs, accelerators, or other device chiplets, the VIP for CHI-C2C provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms.
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Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- 003TSMC_PVT_01 IP library is a unique solution intended to continuously monitor IC status at several on-die locations.
- It is able to detect manufacturing process deviation, perform voltage, current and die temperature measurement.
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USB 20Gbps Device Controller
- Leveraging the benefits of USB 10Gbps and 5Gbps device controller, USB 20Gbps is designed using the FPGA built-in transceiver.
- It is a one-stop solution for all USB requirements ranging from USB 3.2 to USB 2.0.
- It supports SuperSpeed+ (SSP x2/x1), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes.
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SM4 Cipher Engine
- The SM4 IP core implements a custom hardware accelerator for the SM4 symmetric block cipher, specified in Chinese national standard GB/T 32907-2016, and ISO/IEC 18033-3:2010/Amd 1:2021.
- Designed for easy integration, the core, internally expanding the 128-bit key, is capable of both encryption and decryption and features a simple handshake input and output data interface.
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Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- The ODT-ADS-7B64G-3 is an ultra-high-bandwidth time-interleaved ADC designed in a 3nm CMOS process.
- This 7-bit, 64GSPS ADC supports ac-coupled input signals up to Nyquist and features a full-scale range of 0.45Vpp differential, excellent dynamic performance, and low noise operation.
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Fault Tolerant DDR2/DDR3/DDR4 Memory controller
- FTADDR is a memory controller for DDR2,DDR3 and DDR4 SDRAM memory devices.
- It uses a strong error correction code to achieve exceptional fault tolerance
UCIe Controller IP View All
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UCIe Die-to-Die Chiplet Controller
- High configurability and customizability
- Defines packets to communicate with a link partner using different AXI parameters
- Supports raw streaming modes
- Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
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UCIe PHY & D2D Adapter
- 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
- UCIe v1.1 specification
PCIe 7.0 IP View All
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PCIe 7.0 Controller with AXI
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Separate native TX/RX data path separating posted/Non posted/completion traffic
- Handles up to 4 TLPs per cycle
- Advanced PIPE modes and port bifurcation
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PCIe 7.0 PHY IP
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
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PCIe 7.0 PHY in TSMC (N5, N3P)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
- Spread-spectrum clocking (SSC)
AI IP View All
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RISC-V CPU IP
- RISC-V RVA23 Compliant
- >18 SPECint2006/GHz
- 8-wide decode unit
- Advanced branch predictor
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NPU IP for Embedded ML
- Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
- Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
- Future proof architecture that supports the most advanced ML data types and operators
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Future-proof IP for training and inference with leading performance per watt and per dollar
- RISC-V-based AI IP development for enhanced training and inference.
- Silicon-proven solutions tailored for AI workload optimization.
- Energy-efficient performance with industry-leading Perf/W.
MIPI IP View All
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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
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MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
RISC-V IP View All
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32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32/64 Bit RISC-V core
- 5-stage pipeline
- In-order, Single issue
- Multicore Capable (up to 8 cores)
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Dual-issue Linux-capable RISC-V core
- 64-bit RISC-V core
- RVA22 profile
- Linux capable
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High-performance RISC-V CPU
- Fully compliant with the RVA23 RISC-V specification
- Comparable PPA to Arm Neoverse V3 / Cortex-X4
- Standard AMBA CHI.E coherent interface for SoC and chiplet integration
- Co-architected with Veyron E2 for seamless vector, AI acceleration, and big-little style heterogeneous compute configurations