The Semiconductor IP Marketplace

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Spotlight

  • Flash Memory LDPC Decoder IP Core
    • Quasi cyclic (QC) – Algebraic constructed – LDPC Code 
    • Regular Parity Check Matrix 
    • Codeword length: 16 K 
    • Code rate 0.953 
    • No or very low error floor 
    • Parallel/Layered decoding 
  • SLM Signal Integrity Monitor
    • The SLM Signal Integrity Monitor (SIM) IP enables signal quality measurement for die-to-die interfaces. It can be implemented in silicon with minimal area overhead. It enables accurate measurement of silicon interconnects with real-time reporting for analytics.
    • With the use of Monitor, Test and Repair (MTR), this real-time reporting enables structural lane monitoring, aging related degradation, and optional repair of failing lanes to maintain high-speed performance throughout the silicon lifecycle.
    Block Diagram -- SLM Signal Integrity Monitor
  • Digital PUF IP
    • Generate unclonable 128 or 256-bit seeds with a compact, logic-based PUF that drops into any SoC.
    • Digital PUF IP adds true hardware identity for secure boot, key generation, and device authentication with minimal silicon overhead.
  • Embedded USB2 (eUSB) Controller + PHY IP
    • Compliant to Embedded USB2 Version2.0, Aug 2024
    • Supports high-speed, full-speed, and low-speed operation.
    • Meet low voltage requirement (1.0V – 1.2V)
    • No change in existing USB2/USB3 Port
    • Supports symmetric and asymmetric data rates
    Block Diagram -- Embedded USB2 (eUSB) Controller + PHY IP
  • SD4.x UHSII
    • Fully compliant with UHSII specification Ver. 4.x
    • Bidirectional receiver/transmitter (2 channels) supporting both full and half duplex modes
    • Supports data rates from 390Mbps to 1.56Gbps/ch
    • RCLK frequency: 26 to 56MHz
    • Built-in PLL and clock recovery
    Block Diagram -- SD4.x UHSII
  • 1.8V Capable GPIO on Samsung Foundry 4nm FinFET
    • The 1.8V capable GPIO is an IP macro for on-chip integration. It is a 1.8V general purpose I/O built with a stack of 1.2V MOS FINFET devices. It is controlled by 0.75V (core) signals.
    • Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
    Block Diagram -- 1.8V Capable GPIO on Samsung Foundry 4nm FinFET

UCIe Controller IP View All

  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • UCIe Die-to-Die PHY
    • High Bandwidth Density and Data Rates
    • Package Configurability
    • Energy Efficiency
    • Fully Integrated Solution
    Block Diagram -- UCIe Die-to-Die PHY

PCIe 7.0 IP View All

  • PCIe 7.0 Controller with AXI
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Separate native TX/RX data path separating posted/Non posted/completion traffic
    • Handles up to 4 TLPs per cycle
    • Advanced PIPE modes and port bifurcation
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
  • PCIe 7.0 PHY in TSMC (N5, N3P)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SSC)

AI IP View All

  • RISC-V CPU IP
    • RISC-V RVA23 Compliant 
    • >18 SPECint2006/GHz
    • 8-wide decode unit
    • Advanced branch predictor
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
    • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
    • Future proof architecture that supports the most advanced ML data types and operators
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    • RISC-V-based AI IP development for enhanced training and inference.
    • Silicon-proven solutions tailored for AI workload optimization.
    • Energy-efficient performance with industry-leading Perf/W.
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar

MIPI IP View All

RISC-V IP View All

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