The Semiconductor IP Marketplace

Spotlight

• 100G PAM4 Serdes PHY - 14nm

  • The 100G SERDES PHY IP for VSR supports up to 100 Gbps data rate with low-power consumption and a small footprint.
  • It has advanced features such as equalization, and clock and data recovery, ensuring reliable data transmission.
  • The IP can be integrated into a variety of applications such as networking, data centers, and high-performance computing.
  
• Bluetooth Low Energy Subsystem IP

  • The BLE v6.0 Subsystem IP consists of an integrated Controller and Modem paired to a  proprietary RF on T22 ULL.
  • It is ideally suited to ASIC developers or fabless semiconductor companies who want to add BLE functionality without the hassle of dealing with multiple IP vendors or design groups.​
  
• Multi-core capable 64-bit RISC-V CPU with vector extensions

  • The SiFive® Intelligence™ X180 core IP products are designed to meet the increasing requirements of embedded IoT and AI at the far edge.
  • With this 64-bit version, X100 series IP delivers higher performance and better integration with larger memory systems.
  
• EMFI Detector

  • The agileEMSensor is a Ring Oscillator (RO) based sensor designed to detect electromagnetic fault injection (EMFI) attacks on critical circuits.
  • It offers protection against Side-Channel Attacks (SCAs) and tampering through deliberate electromagnetic disturbances.
  • The sensor provides digital outputs to warn processors of intrusion attempts.
• Sine Wave Frequency Generator

  • The Sine Wave Frequency Generator is a time and frequency aligned sine wave frequency generator allowing any frequency to be generated between 1Hz and 200kHz adjustable in 1Hz steps.
  • It uses the vendor's Adjustable Clock core as source for source synchronous frequency generation. It provides either a parallel DAC interface or a serial highly configurable SPI interface to access a DAC.
  
• CAN XL Verification IP

  • The CAN XL Verification IP provides an effective & efficient way to verify the CAN components of an IP or SoC.
  • The CAN XL VIP is fully compliant with CAN XL specifications (CiA 610-1, CiA 610-3, 11898-1 2024, 11898-2 2024, CiA 611-1).
  • The VIP is light weight with easy plug-and-play components so that there is no hit on the design cycle time.
  

UCIe Controller IP View All

• UCIe Die-to-Die Chiplet Controller

  • High configurability and customizability
  • Defines packets to communicate with a link partner using different AXI parameters
  • Supports raw streaming modes
  • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
  
• UCIe PHY & D2D Adapter

  • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
  • UCIe v1.1 specification
  

PCIe 7.0 IP View All

• PCIe 7.0 Controller with AXI

  • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
  • Separate native TX/RX data path separating posted/Non posted/completion traffic
  • Handles up to 4 TLPs per cycle
  • Advanced PIPE modes and port bifurcation
  
• PCIe 7.0 PHY IP

  • Physical Coding Sublayer (PCS) block with PIPE interface
  • Supports PCIe 7.0, encoding, backchannel initialization
  • Lane margining at the receiver
• PCIe 7.0 PHY in TSMC (N5, N3P)

  • Physical Coding Sublayer (PCS) block with PIPE interface
  • Supports PCIe 7.0, encoding, backchannel initialization
  • Lane margining at the receiver
  • Spread-spectrum clocking (SSC)

AI IP View All

• RISC-V CPU IP

  • RISC-V RVA23 Compliant 
  • >18 SPECint2006/GHz
  • 8-wide decode unit
  • Advanced branch predictor
  
• NPU IP for Embedded ML

  • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
  • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
  • Future proof architecture that supports the most advanced ML data types and operators
  
• Future-proof IP for training and inference with leading performance per watt and per dollar

  • RISC-V-based AI IP development for enhanced training and inference.
  • Silicon-proven solutions tailored for AI workload optimization.
  • Energy-efficient performance with industry-leading Perf/W.
  

MIPI IP View All

• MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6

  • Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
  • Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
  
• MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.

  • Fully compliant to MIPI standard
  • Small footprint
  • Code validated with Spyglass
  
• MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)

  • Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
  • Supports standard PHY transceiver compliant to MIPI Specification
  • Supports standard PPI interface compliant to MIPI Specification
  • Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
  

RISC-V IP View All

• 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.

  • 32/64 Bit RISC-V core
  • 5-stage pipeline
  • In-order, Single issue
  • Multicore Capable (up to 8 cores)
  
• Dual-issue Linux-capable RISC-V core

  • 64-bit RISC-V core
  • RVA22 profile
  • Linux capable
  
• High-performance RISC-V CPU

  • Fully compliant with the RVA23 RISC-V specification
  • Comparable PPA to Arm Neoverse V3 / Cortex-X4
  • Standard AMBA CHI.E coherent interface for SoC and chiplet integration
  • Co-architected with Veyron E2 for seamless vector, AI acceleration, and big-little style heterogeneous compute configurations