The Semiconductor IP Marketplace

Spotlight

• HBM4 Memory Controller

  • Supports HBM4 memory devices
  • Supports all standard HBM4 channel densities (up to 32 Gb)
  • Supports up to 10 Gbps/pin
  • Refresh Management (RFM) support
  
• Ultra Low Power AI core

  • Ultra-low power standalone NPU core (<1mW)
  •  Support power islands for minimal standby power
  •  Industry-standard development environment
  
• Controller for MIPI Soundwire

  • MIPI compliant peripheral controller with multi-lane capability
  • APB Peripheral interface for control port and manager configuration registers
  • APB Initiator interface for external user defined registers
  
• Software solution targeting the configuration of Ethernet switches and endpoints in TSN networks

  • Read static topology from YANG compliant custom XML file
  • Read dynamic Traffic Provision Request (TPR) from IEEE 802.1Qdj YANG compliant file
  • Receive TPRs dynamically from CUC as IEEE 802.1Qdj compliant YANG messages (alternatively to above file modes)
  

UCIe Controller IP View All

• UCIe Die-to-Die Chiplet Controller

  • High configurability and customizability
  • Defines packets to communicate with a link partner using different AXI parameters
  • Supports raw streaming modes
  • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
  
• UCIe PHY & D2D Adapter

  • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
  • UCIe v1.1 specification
  
• 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe

  • Efficiency
  • Composability
  • Programmability
  

PCIe 7.0 IP View All

• PCIe 7.0 Controller with AXI

  • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
  • Scalable data path
  • Advanced PIPE modes and port bifurcation
  • Supports multiple virtual channels (VCs) in FLIT and non-FLIT modes
  
• PCIe 7.0 PHY IP

  • Physical Coding Sublayer (PCS) block with PIPE interface
  • Supports PCIe 7.0, encoding, backchannel initialization
  • Lane margining at the receiver
• PCIe 7.0 PHY in TSMC (N5, N3P)

  • Physical Coding Sublayer (PCS) block with PIPE interface
  • Supports PCIe 7.0, encoding, backchannel initialization
  • Lane margining at the receiver
  • Spread-spectrum clocking (SSC)

AI IP View All

• NPU IP for Embedded AI

  • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
  • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
  • Future proof architecture that supports the most advanced ML data types and operators
  
• RISC-V-based AI IP development for enhanced training and inference

  • RISC-V-based AI IP development for enhanced training and inference.
  • Silicon-proven solutions tailored for AI workload optimization.
  • Energy-efficient performance with industry-leading Perf/W.
  
• NPU IP family for generative and classic AI with highest power efficiency, scalable and future proof

  • Support wide range of activations & weights data types, from 32-bit Floating Point down to 2-bit Binary Neural Networks (BNN)
  

MIPI IP View All

• MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6

  • Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
  • Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
  
• MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.

  • Fully compliant to MIPI standard
  • Small footprint
  • Code validated with Spyglass
  
• MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)

  • Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
  • Supports standard PHY transceiver compliant to MIPI Specification
  • Supports standard PPI interface compliant to MIPI Specification
  • Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
  

RISC-V IP View All

• 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.

  • 32/64 Bit RISC-V core
  • 5-stage pipeline
  • In-order, Single issue
  • Multicore Capable (up to 8 cores)
  
• Dual-issue Linux-capable RISC-V core

  • 64-bit RISC-V core
  • RVA22 profile
  • Linux capable
  
• RISC-V high performance CPU

  • Aggressive eight-wide deep out-of-order pipeline
  • Unique 512KB IL2(I-cache) with DL1/DL2 (512KB) split vs unified 1MB L2