The Pulse
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Quintauris 與晶心科技攜手合作,擴展 RISC-V 生態系統
2025-10-14T05:36:00+00:00
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积极拥抱RISC-V+AI,国芯科技高性能汽车智能域控 AI MCU芯片完成设计进入流片试制阶段
2025-10-13T13:46:00+00:00
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晶心科技與 Arculus System 攜手合作將 iPROfiler™ 整合進 AndeSysC 擴展虛擬平台支援助攻 RISC-V SoC 設計
2025-10-13T11:38:00+00:00
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Perceptia pPLL08W 成功应用于智能手机 5G 射频芯片量产流片
2025-10-09T03:04:00+00:00
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創意電子公佈民國114 年9 月份營收報告
2025-10-07T12:07:00+00:00
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安谋科技发布CPU IP “星辰”STAR-MC3,提升传统嵌入式芯片AI处理能力及面效比
2025-09-30T13:35:00+00:00
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国产领军的全功能 GPU “风华3号” 重磅发布,多个第一赋能千行百业人工智能+
2025-09-29T11:11:00+00:00
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Allegro DVT 推出全面合规测试工具,支持 AV2 标准生态系统
2025-09-25T12:38:00+00:00
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锐成芯微推出MIPI A-PHY IP:搭建汽车电子高效数据传输网络
2025-09-25T11:43:00+00:00
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Perceptia Devices 推出 pPLL08N:紧凑型窄带射频锁相环(RF PLL)系列 IP,进一步完善 pPLL08 产品线
2025-09-25T05:00:00+00:00
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芯原推出基于FD-SOI工艺的无线IP平台,支持多样化物联网及消费电子应用
2025-09-24T05:09:00+00:00
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MIPI A-PHY达成里程碑,成为首个获全球汽车OEM采用并进入量产的SerDes标准
2025-09-23T05:40:00+00:00
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Silicon Creations在台积电FinFET工艺上完成第 1000 个项目量产流片,完整 N2 工艺 IP 库同步上线
2025-09-17T12:30:00+00:00
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Perceptia Devices 正式启动将 pPLL03 移植至三星 8 纳米工艺平台
2025-09-11T03:50:00+00:00
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新思科技领先EDA解决方案宣布拓展AI功能
2025-09-11T01:06:00+00:00
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芯測科技完成FMEDA分析 助客戶打造符合ISO 26262的車用 IC
2025-09-10T06:26:00+00:00
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熵碼科技(力旺電子子公司)與科絡達科技策略聯盟: 以PUF技術強化OTA資安防護,布局軟體定義設備時代
2025-09-09T05:53:00+00:00
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創意電子公佈民國114 年8 月份營收報告
2025-09-05T06:27:00+00:00
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IntoPIX 因开发JPEG XS 荣获 2025 艾美奖
2025-09-04T15:30:00+00:00
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让高性能计算芯片设计与CXL规范修订保持同步
2025-09-04T08:33:00+00:00
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Leader 和IntoPIX 通过JPEG XS 集成提升IP 流监控能力
2025-09-04T05:38:00+00:00
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Silicon Creations 荣获 GlobalFoundries 年度模拟混合信号 IP 合作伙伴称号
2025-09-03T14:27:00+00:00
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创意电子 (GUC) 正式加入 NVIDIA NVLink Fusion 生态系统
2025-09-03T05:42:00+00:00
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IntoPIX 和 Arkona Technologies 将下一代IP 广播工作流程的JPEG XS 密度提高一倍
2025-09-02T06:04:00+00:00
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芯来科技发布加解密IP系列与加速器IP系列产品
2025-09-01T06:47:00+00:00
The Semiconductor IP Marketplace that puts you first
Semi IP Hub's mission is to provide you with a platform where you can find Silicon IP cores for your next project without being harassed by dozens of sellers.
Here, your contact details are not shared with third parties unless you request to be contacted by a supplier.
Spotlight
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Power-OK Monitor
- The agilePOK is a Power OK monitor that consists of a voltage reference and comparators to set a programmable high and low threshold level for power supply integrity detection.
- The number of trigger outputs can be customized and each threshold can be adjusted during operation to support DVFS operation.
- This monitor can be used to detect loss of power or attacks to the power supply.
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RISC-V-Based, Open Source AI Accelerator for the Edge
- Coral NPU is a machine learning (ML) accelerator core designed for energy-efficient AI at the edge.
- Based on the open hardware RISC-V ISA, it is available as validated open source IP, for commercial silicon integration.
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Securyzr™ neo Core Platform
- Securyzr™ neo Core Platform is Secure-IC’s enhanced version of its flagship offering Securyzr™ integrated Secure Element (iSE) Series.
- Thanks to its common platform, the entire Securyzr™ neo Series is now faster and more optimized than ever.
- With an optimal Power Performance Area (PPA), Secure-IC is offering a more comprehensive and mature solution to address all security needs from the different applications: spanning from IoT, Factory Automation, AIoT, Automotive, Cloud & Datacenter, to Mobile.
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112G Multi-SerDes
- Designed with a small footprint, ultra-low latency, and low power consumption, the 112G SerDes maximizes bidirectional memory access efficiency, reduces software complexity, and helps chip developers leverage existing Ethernet infrastructure to significantly lower Total Cost of Ownership (TCO).
- Featuring IEEE 802.3-compliant Forward Error Correction (FEC), 35dB ultra-high channel loss compensation, and adaptive high-speed equalization technologies (CTLE, FFE), it provides full-cycle link protection—from error correction to pre-warning—enabling highly compatible, stable, and efficient chip-to-chip connectivity solutions.
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SHA3 Cryptographic Hash Cores
- Completely self-contained; does not require external memory
- SHA3-224, SHA3-256, SHA3-384, and SHA3-512 support SHA-3 algorithms per FIPS 202.
- SHAKE128 / SHAKE256 XOF support is included.
- Flow-through design; flexible data bus width
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ISO/IEC 7816 Verification IP
- The ISO/IEC 7816 Verification IP offers a streamlined and efficient solution for verifying System-on-Chip (SoC) and IP designs that incorporate contactless communication.
- The ISO/IEC 7816 VIP is compliant with ISO/IEC 7816 Specifications. This VIP is light weight with easy plug-and- play interface so that there is no hit on the design cycle time.
UCIe Controller IP View All
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UCIe Die-to-Die Chiplet Controller
- High configurability and customizability
- Defines packets to communicate with a link partner using different AXI parameters
- Supports raw streaming modes
- Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
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UCIe PHY & D2D Adapter
- 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
- UCIe v1.1 specification
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TSMC CLN5FF GUCIe LP Die-to-Die PHY
- IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
- This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the
PCIe 7.0 IP View All
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PCIe 7.0 Controller with AXI
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Separate native TX/RX data path separating posted/Non posted/completion traffic
- Handles up to 4 TLPs per cycle
- Advanced PIPE modes and port bifurcation
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PCIe 7.0 PHY IP
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
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PCIe 7.0 PHY in TSMC (N5, N3P)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
- Spread-spectrum clocking (SSC)
AI IP View All
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RISC-V CPU IP
- RISC-V RVA23 Compliant
- >18 SPECint2006/GHz
- 8-wide decode unit
- Advanced branch predictor
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NPU IP for Embedded ML
- Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
- Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
- Future proof architecture that supports the most advanced ML data types and operators
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Future-proof IP for training and inference with leading performance per watt and per dollar
- RISC-V-based AI IP development for enhanced training and inference.
- Silicon-proven solutions tailored for AI workload optimization.
- Energy-efficient performance with industry-leading Perf/W.
MIPI IP View All
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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
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MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
RISC-V IP View All
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32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32/64 Bit RISC-V core
- 5-stage pipeline
- In-order, Single issue
- Multicore Capable (up to 8 cores)
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Dual-issue Linux-capable RISC-V core
- 64-bit RISC-V core
- RVA22 profile
- Linux capable
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High-performance RISC-V CPU
- Fully compliant with the RVA23 RISC-V specification
- Comparable PPA to Arm Neoverse V3 / Cortex-X4
- Standard AMBA CHI.E coherent interface for SoC and chiplet integration
- Co-architected with Veyron E2 for seamless vector, AI acceleration, and big-little style heterogeneous compute configurations