The Semiconductor IP Marketplace

Spotlight

• MIPI SoundWire I3S Peripheral IP

  • The MIPI SoundWire I3S Peripheral IP delivers seamless, low-power, and high-quality audio connectivity for a range of mobile, consumer, and automotive devices.
  • Fully compliant with the MIPI SoundWire I3S (Inter-IC Sound) specifications, it enables synchronized, multi-channel audio communication with a compact and efficient two-wire interface, ideal for integrating digital microphones, amplifiers, or audio codecs.
  
• ML-DSA Digital Signature Engine

  • The KiviPQC™-DSA is a hardware accelerator for post-quantum cryptographic operations.
  • It implements the Module Lattice-based Digital Signature Algorithm (ML-DSA), standardized by NIST in FIPS 204.
  • This mechanism realizes the appropriate procedures for securely generating a private/public key pair, digitally signing a message or a data block, and performing digital signature verification. 
  
• P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core

  • Small size: From 70K ASIC gates (at throughput of 18.2 bits per clock)
  • 500 MHz frequency in 90 nm process
  • Easily parallelizable to achieve higher throughputs
  • Completely self-contained: does not require external memory. Includes encryption, decryption, key expansion and data interface
  
• LPDDR6/5X/5 Controller IP

  • Supports JEDEC standard LPDDR6, LPDDR5X and LPDDR5 SDRAMs
  • Support for data rates up to 14.4 Gbps for LPDDR6, 10.67 Gbps for LPDDR5X, and 6.4 Gbps for LPDDR5
  • Multiport Arm® AMBA® interface AXI™4 with managed QoS or single-port host interface to the DDR controller
  • DFI 5.2 compliant interface to Synopsys LPDDR6/5X/5 PHY
  
• Post-Quantum ML-KEM IP Core

  • Efficient Performance
  • SCA/FIA Protections
  • Patented High-Performance Modulo Multiplication
  • Flexible Interfaces
• MIPI SoundWire I3S Manager IP

  • The MIPI SoundWire I3S Manager IP enables efficient, low-power, and high-fidelity audio data transfer for mobile, consumer, and automotive applications.
  • Compliant with the MIPI SoundWire I3S (Inter-IC Sound) standards, it supports synchronized, multi-channel audio over a scalable two-wire interface, ideal for connecting digital microphones, amplifiers, and codecs in space-constrained designs.
  

UCIe Controller IP View All

• UCIe Die-to-Die Chiplet Controller

  • High configurability and customizability
  • Defines packets to communicate with a link partner using different AXI parameters
  • Supports raw streaming modes
  • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
  
• UCIe PHY & D2D Adapter

  • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
  • UCIe v1.1 specification
  
• TSMC CLN5FF GUCIe LP Die-to-Die PHY

  • IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
  • This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the
  

PCIe 7.0 IP View All

• PCIe 7.0 Controller with AXI

  • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
  • Separate native TX/RX data path separating posted/Non posted/completion traffic
  • Handles up to 4 TLPs per cycle
  • Advanced PIPE modes and port bifurcation
  
• PCIe 7.0 PHY IP

  • Physical Coding Sublayer (PCS) block with PIPE interface
  • Supports PCIe 7.0, encoding, backchannel initialization
  • Lane margining at the receiver
• PCIe 7.0 PHY in TSMC (N5, N3P)

  • Physical Coding Sublayer (PCS) block with PIPE interface
  • Supports PCIe 7.0, encoding, backchannel initialization
  • Lane margining at the receiver
  • Spread-spectrum clocking (SSC)

AI IP View All

• RISC-V CPU IP

  • RISC-V RVA23 Compliant 
  • >18 SPECint2006/GHz
  • 8-wide decode unit
  • Advanced branch predictor
  
• NPU IP for Embedded ML

  • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
  • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
  • Future proof architecture that supports the most advanced ML data types and operators
  
• Future-proof IP for training and inference with leading performance per watt and per dollar

  • RISC-V-based AI IP development for enhanced training and inference.
  • Silicon-proven solutions tailored for AI workload optimization.
  • Energy-efficient performance with industry-leading Perf/W.
  

MIPI IP View All

• MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6

  • Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
  • Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
  
• MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.

  • Fully compliant to MIPI standard
  • Small footprint
  • Code validated with Spyglass
  
• MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)

  • Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
  • Supports standard PHY transceiver compliant to MIPI Specification
  • Supports standard PPI interface compliant to MIPI Specification
  • Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
  

RISC-V IP View All

• 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.

  • 32/64 Bit RISC-V core
  • 5-stage pipeline
  • In-order, Single issue
  • Multicore Capable (up to 8 cores)
  
• Dual-issue Linux-capable RISC-V core

  • 64-bit RISC-V core
  • RVA22 profile
  • Linux capable
  
• High-performance RISC-V CPU

  • Fully compliant with the RVA23 RISC-V specification
  • Comparable PPA to Arm Neoverse V3 / Cortex-X4
  • Standard AMBA CHI.E coherent interface for SoC and chiplet integration
  • Co-architected with Veyron E2 for seamless vector, AI acceleration, and big-little style heterogeneous compute configurations