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Decision tree inference core
- So_ip_idt core can be used create a decision tree directly in hardware. It can create DTs with univarite, multivariate and non-linear tests.
- Creating DTs directly in hardware results in the significant increase of DT inference speed, compared with the traditional software-based approach.
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FPGA Scrubber Controller
- GRSCRUB is an FPGA supervisor responsible for programming and scrubbing the FPGA configuration memory to prevent the accumulation of radiation-induced errors.
- The GRSCRUB IP currently supports the AMD/Xilinx Kintex UltraScale and Virtex-5 FPGA families.
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3D LUT Intel® FPGA IP
- As a part of the Video and Vision Processing (VVP) Suite Intel® FPGA IP, the 3D look-up table (LUT) Intel® FPGA IP provides an efficient solution for video color space and dynamic range conversions, chroma keying, and the creation of artistic effects.
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ARINC429 Verification IP
- Available in Verilog, System Verilog, and UVM.
- Support for Bipolar RZ encoding
- Integration friendly
- Supports a wide variety of error injection scenarios.
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ARINC 708A Verification IP
- Available in Verilog, System Verilog, and UVM.
- Control Word information can be user-configurable / Random. (Protected By parity).
- Data word header will be according to the 270 271 label Frame received from Control Word.
- Support for Hazards, Faults, and Errors.
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I3C
- Innosilicon’s I3C (Improved Inter Integrated Circuit) is enhanced with I2C protocol and is compatible with I2C
- It adds new functions, including higher transmission speed, in-band interrupt, CRC check, and so on
- Now, the I3C protocol is divided into MIPI and JEDEC
- Usually, MIPI I3C is applied in sensor/IoT data transmission, and JEDEC I3C is applied in storage chip configuration
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Ultra-low-power 60 GHz radar-on-chip
- CSEM has developed a low-cost, ultra-low-power 60 GHz MIMO FMCW PHY that can be integrated into radar-on-chips with custom digital processing for specific applications.
- This solution leverages CSEM’s decades of experience in ultra-low-power RF CMOS system-on-chip design.
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cjTAG IEEE 1149.7 Compact TAP Controller
- Supports IEEE 1149.7 classes 0–5 (selected through hardware configuration parameter)
- Partitioned along IEEE 1149.7-specified functional boundaries (so that only the required hardware is included):
- Supports all mandatory and optional scan formats: JScan0–3, SScan0–3, OScan0–7, and MScan
- Supports all mandatory and optional cJTAG commands
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LZ4/Snappy Data Decompressor
- LZ4SNP-D is a custom hardware implementation of a lossless data decompression engine for the LZ4 and Snappy compression algorithms.
- The core receives compressed files, automatically detects the LZ4 or Snappy format, and outputs the decompressed data.
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xHCI Verification IP
- Compliant with xHCI 1.1, USB3.1, USB3.0, USB2.0 (including errata) and PIPE specifications 3.0, UTMI+ 1.1, ULPI 1.1 specifications.
- Full support for backward compatibility (HS/FS/LS).
- Flexible user interface : AHB/AXI/PCIe with configurable Data width (32,64,128).
- Supports upto 64 device slots, 2 downstream ports and upto 4 interrupters.
