IP Catalog > Analog IP > Power Management IP

Power Management IP

Power management IPs are indispensable in modern chip design, especially for battery applications where power is constrained and for high-power applications where thermal efficiency is vital. Power management IPs are specialized blocks or circuits that help to control the power consumption, voltage levels and energy efficiency of a system.

Power Management IP, such as Low Drop-Out (LDO) Regulators, Power-On-Reset (POR) Monitors, and the Power Management Unit (PMU) Subsystem, ensure low power consumption with optimal performance.

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Compare 900 Power Management IP from 52 vendors (1 - 10)
  • 50 mA LDO voltage regulator (output voltage 0.9V/1.2V/1.34V) on Samsung 65nm
    • 065SAM_LDO_01 is a low drop out voltage regulator designed to supply integrated circuits with stable and precise voltage.
    • The LDO inputs voltage AVD from 1.8V to 5.5V and converts this voltage into a voltage VOUT 0.9V/1.2V/1.35V with 50mA load capacity.
    • A Regulation OK (ROK) signal inform the system that LDO has completed its booting sequence and if its output is maintaining regulation for the current drawn by the load.
    Block Diagram -- 50 mA LDO voltage regulator (output voltage 0.9V/1.2V/1.34V) on Samsung 65nm
  • Adaptive Body Bias Generator on Samsung 28nm LN28FDS
    • The adaptive body bias generator (ABBG) consists of a positive-BBG and a negative-BBG for FDSOI-MOS transistors.
    • The ABBG is used for either Reverse Body Biasing (RBB) to reduce leakage current of the logic devices or Forward Body Biasing (FBB) to improve the system performance by adjusting the body voltages of transistors.
    Block Diagram -- Adaptive Body Bias Generator on Samsung 28nm LN28FDS
  • 16mA 4V Voltage Regulator
    • The TS_VR_4V00_X8 is a 4V voltage regulator capable of delivering up to 16mA. It is required for the supply of other TES IPs like TS_FS_9M70_X8,
    • TS_VA_LNDC_X8, and TS_CS_20uA_X8. The TS_VR_4V00_X8 operates with one supply voltage, VDDA5, VDDIO (5V typical) and one precision reference voltage VREF (2.5V).
    Block Diagram -- 16mA 4V Voltage Regulator
  • Octuple 20uA Bias Current Source

    • The TS_CS_20uA_X8 is a current generator sourcing 20µA via each terminal IBPU<0> through IBPU<7>, for the biasing of other TES IPs like TS_FS_9M70_X8 and TS_VA_LNDC_X8 (for the latter IP, its input reference current must be mirrored from one Bias output by a simple cascoded NMOS circuit)

    Block Diagram -- Octuple 20uA Bias Current Source
  • Body bias voltage generator - GLOBALFOUNDRIES 22FDX
    • The ABX Generator IP is a body bias voltage generator for the ABX Platform for GLOBALFOUNDRIES 22FDX® technology.
    • It contains a closed loop body bias regulation loop to generate N-well and P-well bias voltages for adaptive compensation of process, voltage and temperature (PVT) variations during device operation.
    Block Diagram -- Body bias voltage generator - GLOBALFOUNDRIES 22FDX
  • Power and Clock Generation IP - GLOBALFOUNDRIES® 22FDX®
    • Tightly integrated power management platform with a soft-IP wrapper around Analog / Mixed-Signal hard macros which generate all supply voltages and clock signals needed to run highly efficient SoCs in GlobalFoundries® 22FDX®.
    • Running from only one supply voltage and reference clock, the IP generates its own internal supplies and references, and those needed to run the Racyics® ABX® Generator.
    Block Diagram -- Power and Clock Generation IP - GLOBALFOUNDRIES® 22FDX®
  • Adaptive Body Biasing Generator - GLOBALFOUNDRIES 22FDX
    • RI_ABB_GF22FDX is a cutting-edge adaptive body bias (ABB) generator for GLOBALFOUNDRIES® 22FDX® technology.
    • Featuring patented closed control loops with independent N-well and P-well body bias voltage generation, this silicon-proven IP dynamically compensates for process, voltage, and temperature (PVT) variations during operation.
    Block Diagram -- Adaptive Body Biasing Generator - GLOBALFOUNDRIES 22FDX
  • Power-On-Reset IP
    • The Power-On-Reset (POR) IP provides reliable reset functions for general applications
    • It is powered by analog supply and monitors both analog and digital supply
    • The POR IP generates a POR signal to reset the digital logic
    Block Diagram -- Power-On-Reset IP
  • Low Noise, High PSRR, Replica LDO
    • The WEALDORP18NI12RRSP22M22G is a voltage regulator operating from 1.8 V voltage supply
    • The WEALDO18NI12SFN12M22G provides one output voltage 1.2 V driving output load that sinks specific current
    Block Diagram -- Low Noise, High PSRR, Replica LDO
  • Low Noise, High PSRR, Replica LDO
    • The WEALDORP1812NI8SFN12M22G is a low-dropout regulator LDO with voltage supplies 1.8 V and 1.2 V
    • The WEALDORP1812NI8SFN12M22G gives one output voltage 1.2 V driving the Power Amplifier
    • The output is programmable to retain the output voltage constant when the load current varies under a wide range.
    Block Diagram -- Low Noise, High PSRR, Replica LDO
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