DSP & Math IP

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Compare 819 DSP & Math IP from 98 vendors (1 - 10)
  • 66/2112 Codec for Cyclic Code (2112,2080)
    • Small Size
    • Implements FEC Sublayer for 10GBASE-R (section 74 of the IEEE 802.3 standard)
    • 10G/40G/100G Ethernet MAC-friendly interface
    • Practically self-contained: requires only memory for one 2112-bit block in the decoder.
    Block Diagram -- 66/2112 Codec for Cyclic Code (2112,2080)
  • 2.5 Gbps GPON FEC Codec
    • This high performance core is a full featured Forward Error Correction encoder and decoder, specially designed for high speed optical networks or any other broadband applications.
    • It is fully compliant with the 2.5 Gbps GPON standard (G.984.3) and is available for FPGA or ASIC implementation.
    • The FEC algorithm is based on Reed-Solomon (255,239) code and consists of an encoder and decoder module.
    Block Diagram -- 2.5 Gbps GPON FEC Codec
  • WCDMA Release 9 compliant Viterbi Decoder
    • 3GPP TS 25.212 V 9.5.0 Release 9
    • Supports all block sizes i.e., K=40 - 504.
    • Constraint length of 9
    Block Diagram -- WCDMA Release 9 compliant Viterbi Decoder
  • Block Diagram -- Error Correction IP
  • DVB-S2X Wideband Modulator
    • Compliant with DVB-S2 and DVB-S2X
    • Supports ACM, CCM, and VCM modes
    • Support for short and normal frames (16,200 bits and 64,800 bits)
    • Support for QPSK to 256-APSK, VLSNR modes on request
    Block Diagram -- DVB-S2X Wideband Modulator
  • DVB-GSE Encapsulator and Decapsulator
    • The DVB-GSE encapsulator and decapsulator IP cores close the gap between network protocols like Ethernet and the physical layer of the DVB family of standards.
    • The DVB-GSE encapsulator performs the encapsulation of the network layer packets, also referred to as Protocol Data Units (PDUs), into one or more GSE packets, adding control information and performing integrity checks when necessary. 
    Block Diagram -- DVB-GSE Encapsulator and Decapsulator
  • DVB-Satellite FEC Decoder
    • The CMS0077 Satellite FEC Decoder has been designed specifically to meet the requirements of the DVB-S2 and DVB-S2X advanced wide-band digital satellite standards.
    • The core provides all the necessary processing steps to convert a demodulated complex I/Q signal into a standard TS output stream.
    Block Diagram -- DVB-Satellite FEC Decoder
  • oFEC Encoder and Decoder
    • OpenROADM oFEC (Open Forward Error Correction) is a core element of the OpenROADM initiative, providing a standardized, open-source FEC solution for high-speed coherent optical networks.
    • The oFEC IP cores deliver high coding gain through a fully parallel, pipelined decoder architecture with 3 soft-decision (SD) and 2 hard-decision (HD) decoding steps. It supports data rates from 200G to 800G, including Probabilistic Constellation Shaping (PCS) modes to enhance spectral efficiency, noise tolerance, and transmission reach.
    Block Diagram -- oFEC Encoder and Decoder
  • SDA OCT Encoder and Decoder
    • ​Compliant with "Optical Communications Terminal (OCT) Standard Version 3.0, Document ID: SDA-9100-001-05, August 2021"
    • Compliant with "Optical Communications Terminal (OCT) Standard Version 3.1.0, Document ID: SDA-9100-001-08, March 2024"
    • Compliant with "Optical Communications Terminal (OCT) Standard Version 4.0.0, Document ID: SDA-9100-001-09, August 2024"
    Block Diagram -- SDA OCT Encoder and Decoder
  • DVB-S2-LDPC-BCH IP
    • Irregular parity check matrix
    • Layered Decoding
    • Minimum sum algorithm
    • Soft decision decoding
    Block Diagram -- DVB-S2-LDPC-BCH IP
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