DSP & Math IP
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DSP & Math IP
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SDA OCT V3.0 Encoder and Decoder
- Compliant with "Optical Communications Terminal (OCT) Standard Version 3.0, Document ID: SDA-9100-0001-05, August 2021"
- Support for payload code rates 11/13, 22/29, 2/3, 1/2, and uncoded data
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IEEE 802.3bj Reed-Solomon Encoder and Decoder
- Compliant with IEEE 802.3bj, Clause 91
- Support for KR4 (528, 514) and KP4 (544, 514) Reed-Solomon (RS) code
- Corrects up to seven (KR4) or up to 15 (KP4) erroneous symbols
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NCR Processor
- NCR (Network Clock Reference) is a procedure to provide the master clock (i.e. time information) of the satellite to all its user terminals.
- Typically, NCR packets are provided periodically over a continuous DVB-S2 or DVB-S2X link.
- The receiving user terminal uses the knowledge of the master clock in the system to determine when it is allowed to transmit data in a time-division multiple access (TDMA) system, such as DVB-RCS or DVB-RCS2.
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DVB-GSE Encapsulator and Decapsulator
- The DVB-GSE encapsulator and decapsulator IP cores close the gap between network protocols like Ethernet and the physical layer of the DVB family of standards.
- The DVB-GSE encapsulator performs the encapsulation of the network layer packets, also referred to as Protocol Data Units (PDUs), into one or more GSE packets, adding control information and performing integrity checks when necessary.
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OFDM - Orthogonal Frequency Division Multiplexing
- Configure and create complete multiple OFDM Frames with Preamble, Header, and Payload
- Preset for Standard compliant Frames for various wireless standards like Wi-Fi, WiMAX
- Define Frame with Preamble, Header, and Payload (selectively) to simulate different OFDM signals
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LDPC Decoder for 5G NR and Wireless
- The 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance.
- It employs the Min-Sum LDPC decoding algorithm to ensure efficient decoding.
- The core allows for programmable internal bit widths at compile time, though the default values are usually sufficient.
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LDPC Encoder/Decoder (LDPC)
- Supporting a wide range of data-rates
- 50MB/s to 4.0GB/s for a single LDPC instance
- Scalable platform provides the basis for customer specific custom-LDPC cores
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eMMC LDPC Encoder/Decoder
- Supports data rates from 50 MB/s to 9.0 GB/s.
- Enables custom LDPC core development for specific requirements.
- Wide range of codeword sizes.
- Maximum supported parity.
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APB Pulse Width Modulator
- The APB PWM Module is a standard APB peripheral that generates a programmable duty cycle output signal.
- The frequency of the output waveform is either PCLK/256 or PCLK/4096, depending on whether a 4-bit prescaler is enabled.
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Radar processing IP suite for Advanced Driver Assistance Systems
- The eSi-ADAS™ is a suite of radar accelerator IP including a complete Radar co-processor engine, they enhance the overall performance and capabilities of radar systems for automotive, drone and UAV applications that require fast and responsive situational awareness.
- The IP has been licensed to some of the leading automotive Tier 1 and Tier 2 suppliers and is in production vehicles.
