DSP & Math IP

Compare 828 DSP & Math IP from 105 vendors (1 - 10)

32-512 Point Streaming FFT Core
- Supports 32/64/128/256/512-point complex FFT and IFFT and can switch dynamically
- Inputs and outputs data in the natural order
- Throughput of 1 sample (In-phase I + quadrature Q) per 4 clocks; no-gap processing of the input data
- Parameterized bit width.
128-Point FFT/IFFT IP Core
- The FFT4T core implements a 128 point complex FFT and IFFT over 12 data streams in hardware. It runs at the clock frequency four times higher than the insput sampling frequency.
- FFT4T core is a specialized FFT/IFFT processor intended for a situation where an RF signal is recieved over multiple channels in parallel and its filtering is to be performed in the frequency domain. The core fits nicely into, for example, a multichannel GPS system.
DVB-S2-LDPC-BCH
- Irregular parity check matrix
- Layered decoding
- Minimum sum algorithm
- Soft decision decoding
- BCH decoder works on GF (2m) where m=16 or 14 and corrects up to t errors, where t = 8, 10 or 12
ASIP-1 FFT Engine
- Platform to design Application Specific Instruction Set Processors (ASIPs).
- Ideal for supporting multi-standard systems.
- Supports a wide range of complex DSP functions.
ASIP-2 Programmable Filter Engine
- Platform to design Application Specific Instruction Set Processors (ASIPs).
- Ideal for supporting multi-standard systems.
- Supports a wide range of complex DSP functions
- The ASIP2 performs Fast Fourier Transform (FFT) to convert time domain signals to frequency domain signals for further processing. It supports FFT sizes from 4 to 8K.
MIMO Decoder
- Includes QR Decomposition, Dynamic scale and K-best Decoder
- Fixed Depth K-Best Decoder (K=16)
- Achieves close-to ML BER performance
- Supports synchronized streams with different QAM (from BPSK to 64 QAM) dependent on MIMO mode
- Supports square and non-square QAM
MIMO Sphere Decoder
- Fixed Complexity Sphere Decoder providing fixed throughput
- Achieves close-to ML BER performance
- MATLAB and C model for – MIMO 2×2 and 4×4 – Can be modified to support other MIMO sizes – BPSK, 4-QAM, 16-QAM and 64-QAM
- Efficient and optimized FPGA Architecture (4×4 MIMO, 16-QAM)
BCH Decoder
- BCH decoder compliant with the DVB-T2/S2 standard.
- Available for Altera/Xilinx FPGA or ASIC implementation.
- High speed design.
- BCH decoder works on GF(2^M) where M = 16 or 14 and correctup to T errors where T = 10 or 12.
- Area and power optimized implementation.
LDPC Decoder IS-GPS-800D
- Irregular parity check matrix
- Layered Decoding
- Minimum sum algorithm
- Configurable number of iterations
- Soft decision decoding
Reed Solomon
- High performance Reed Solomon IP Core (Encoder and Decoder).
- Supports error and erasure decoding.
- Parameterized codeword length.
- Code generator polynomial: (x + λ^0 )(x + λ^1 )(x + λ^2 )...(x + λ^15 ).