DSP & Math IP

Compare 812 DSP & Math IP from 99 vendors (1 - 10)

Parameterizable compact BCH codec
- Highly parameterizable
- Very low area (in the largest, n = 511 t = 16 configuration, the core uses just 17K gates in ASIC)
- Entirely self-contained (no external RAM required)
MixedRadix FFT IP Core
- The MixedRadix FFT IP Core uses a modular combination of radix2, 3, 5, and 7 Fast Fourier Transform (FFT) pipelined engines to provide discrete transforms on data frames or continuous data streams, with sample rate up to the maximum clock frequency.
- The engines are arranged to provide the most beneficial resource usage and data ordering for the system.
UltraLong FFT
- The UltraLong FFT IP Core uses an efficient Fast Fourier Transform (FFT) algorithm to provide multimillion-point discrete transforms on data frames or continuous data streams.
- This structure utilizes state-of-the-art off-chip memory technology and N1- and N2-length pipelined radix-2 FFT engines with an additional rotation stage to perform N=N1xN2 transform lengths, from 1K to 64M points.
Pipelined Floating Point FFT IP Core
- Any radix-2 length
- Variable length option for runtime per-transform length select
- Clock rates to 400MHz in Virtex-5
- Fixed or floating point math
12-bit 250MHz Decimation filter with 43 taps
- Programmable Coefficients
- Programmable gain/attenuation at the output
- 4X Decimation Factor
12-bit 250MHz interpolation filter with 43 taps on TSMC 16nm
- The ODT-DSP-INT-43T250M-T16 is a 12-bit 250MHz interpolation filter with 43 taps in a 12/16nm CMOS process.
- The 43 Tap interpolation filter increases output data rate (fDOUT) to the DAC by four relative to its original input data rate(fDIN).
66/2112 Codec for Cyclic Code (2112,2080)
- Small Size
- Implements FEC Sublayer for 10GBASE-R (section 74 of the IEEE 802.3 standard)
- 10G/40G/100G Ethernet MAC-friendly interface
- Practically self-contained: requires only memory for one 2112-bit block in the decoder.
2.5 Gbps GPON FEC Codec
- This high performance core is a full featured Forward Error Correction encoder and decoder, specially designed for high speed optical networks or any other broadband applications.
- It is fully compliant with the 2.5 Gbps GPON standard (G.984.3) and is available for FPGA or ASIC implementation.
- The FEC algorithm is based on Reed-Solomon (255,239) code and consists of an encoder and decoder module.
WCDMA Release 9 compliant Viterbi Decoder
- 3GPP TS 25.212 V 9.5.0 Release 9
- Supports all block sizes i.e., K=40 - 504.
- Constraint length of 9
Error Correction IP

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