DSP & Math IP
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4-Quadrant Arctan Function
- ATAN2_XY calculates the 4-quadrant inverse tangent in the range -π to π. It has a fully pipelined architecture and uses fixed-point mathematics throughout.
- Input values are accepted as 12-bit signed numbers in the range -2048 to 2047.
- The calculated output phase (in radians) is a 19-bit signed value with 1 sign bit, 2 integer bits and 16 fractional bits.
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Arctan Function
- ATAN_X calculates the inverse tangent of a fraction. It has a fully pipelined architecture and uses fixed-point mathematics throughout.
- Input values are accepted as 16-bit unsigned fractions in the range 0 to 1. Output values are 16-bit unsigned fractions in the range 0 to π/4.
- Both input and output values are in [16 16] format with 0 integer bits and 16 fraction bits.
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32-bit Floating-point Square-root IP Core
- High-speed fully pipelined 32-bit floating-point square-root function based on the IEEE 754 standard. Features a generic latency from 2 to 24 clock cycles.
- Ideal for floating-point pipelines, arithmetic units and processors.
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32-bit Floating-point Divider IP Core
- High-speed fully pipelined 32-bit floating-point divider based on the IEEE 754 standard.
- Features a generic latency from 2 to 49 clock cycles.
- Ideal for floating-point pipelines, arithmetic units and processors.
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Manchester Encoder / Decoder
- The MAN_CODEC IP Core is a versatile encoder and decoder pair that converts a basic NRZ bitstream into a standard Manchester code and vice-versa.
- The encoder and decoder are provided as separate IP Cores and, as such, may be used independently or together as a combined codec unit.
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RF Power Amplifier Precorrection System
- DPSYS is a complete Digital Precorrection (Predistortion) system designed to compensate for the non-linear characteristic of a high-power RF Amplifier.
- The system is capable of adjusting both the gain and phase of a complex input signal.
- This is achieved by means of a complex multiplication of the input with a complex polynomial function stored in the LUT. Complex inputs are sampled on the rising edge of clk when en is high.
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Direct Digital Synthesizer / Periodic waveform generator
- The DDS IP Core is a high-precision Direct Digital Synthesizer2 used for the generation of periodic waveforms.
- On each rising-edge of the sample clock and when the clock-enable is high, the phase in the phase accumulator is incremented by the value phase_inc.
- This phase is quantized to 16-bits and passed as an address to a look-up table which converts the phase into a waveform.
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IIR Filter Second-Order-Section
- 2nd order IIR filter sometimes referred to as a 'bi-quad'.
- Internally, it has a fully pipelined architecture permitting the highest possible sample rates for IIR filtering.
- The SOS block is modular allowing any number of SOS blocks to be joined in series to implement higher order IIR filters.
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Generic high-speed FIR Filter with symmetry
- FIR filter designed for high sample rate applications with symmetrical coefficients and an even or odd number of taps.
- Features configurable coefficients and data width. Design uses only half the number of multipliers compared to a normal FIR implementation.
- Matlab®, FDAtool and Simulink® compatible.
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Generic ultra-speed FIR Filter
- FIR filter designed for very high sample rate applications up to 600 MHz.
- Organized as a systolic array, the filter is modular and scalable, permitting the user to specify large order filters without compromising maximum attainable clock-speed. Matlab®, FDAtool and Simulink® compatible.
