Peripheral IP
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Sine Wave Frequency Generator
- The Sine Wave Frequency Generator is a time and frequency aligned sine wave frequency generator allowing any frequency to be generated between 1Hz and 200kHz adjustable in 1Hz steps.
- It uses the vendor's Adjustable Clock core as source for source synchronous frequency generation. It provides either a parallel DAC interface or a serial highly configurable SPI interface to access a DAC.
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ARINC 429 IP
- The M429GEN IP implements a synchronous single-chip ARINC 429 Transmit and Receive Controller capable of linking one CPU to one or several ARINC 429 bus.
- The IP controls all ARINC 429 bus specific sequences, protocol and timing. The M429GEN IP interface allows the parallel-bus microprocessor to communicate bidirectionally with the ARINC 429 bus.
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Universal Timers System
- The Universal Timers System is a programmable and highly configurable device that comprises seven submodules: Pulse Width Modulation (PWM), Timer 1, Timer 2, Timer 3, Real-Time Interrupt (RTI), Computer Operates Properly (COP), Pulse Accumulator (PA)
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AMBA AHB 3 Lite Verification IP
- The AMBA 3 AHB-Lite Verification IP provides an effective & efficient way to verify the components interfacing with AMBA®3 AHB-Lite bus of an IP or SoC.
- The AMBA 3 AHB-Lite VIP is fully compliant with standard AMBA 3 AHB-Lite specification from ARM.
- This VIP is a light weight VIP with easy plug-andplay interface so that there is no hit on the design cycle time.
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AMBA AXI3 Verification IP
- The AMBA AXI3 Verification IP provides an effective & efficient way to verify the components interfacing with AMBA® AXI3 bus of an IP or SoC.
- The AMBA AXI3 VIP is fully compliant with standard AMBA® AXI3 specification from ARM.
- This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design cycle time.
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xSPI + eMMC Combo PHY IP
- This IP integrates both xSPI (Expanded Serial Peripheral Interface) and eMMC 5.1 PHY (Physical Layer) into a single unified solution, enabling support for two distinct memory protocols within the same IP.
- By combining the PHY layers for both interfaces, the design simplifies system integration, reduces area and pin count, and enhances design flexibility for SoCs that require both boot and high-speed storage functionality.
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UART to I2C Bridge Controller
- The BRIDGE_UART_I2C IP Core provides a simple and convenient way to interface a standard UART bus to a standard I2C bus.
- The circuit operates as a completely transparent ‘bridge’ between the two buses and allows I2C peripherals to be programmed using a set of basic commands over a (UART) serial interface.
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Sony Camera LVDS Interface
- The SONY_CAM_IF IP Core provides a simple way to connect the Sony® FCB-EV range of cameras to your FPGA.
- It serves as a direct replacement for an external LVDS receiver IC and takes advantage of the fast LVDS I/O solutions provided by modern FPGA devices.
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SPI Slave Serial Interface Controller
- The SPI_SLAVE IP Core is an SPI compliant slave interface controller. The controller decodes the bus signals and de-serializes them into a series of 8-bit bytes.
- Communication with the slave controller is achieved by programming a single control register and a single address register.
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8b/10b Encoder/Decoder
- The CODEC_8B10B IP Core is a scalable 8B/10B Encoder/Decoder pair suitable for a wide range of serial data transmission applications.
- The design is optimized for very high-speed operation and is suitable for use in serial data links of 6 GHz+ on basic FPGA devices.
