Peripheral IP

• The AXI Bridge with DMA IP core is the ultimate PCIe DMA IP solution with a powerful mix of multiple industry standard AXI Interfaces.
• AXI Stream interfaces allow continuous data streaming from FPGA to Host or from Host to FPGA. S-AXI Memory mapped interfaces allow easy data access of remote memories in order to realize shared memory access or per to peer applications.

• The Multi-Channel AXI DMA engine IP Core for AXI4 is a powerful programmable AXI Stream to AXI memory mapped bridge with sophisticated data addressing options.
• These features allow data accesses on a tile basis in order to address regions of interest (ROI) based applications like stereo cameras, 2D picture compression algorithms and others.

• The AXI Bridge for PCIe IP core is the  IP solution with a powerful mix of multiple industry standard memory mapped AXI Interfaces.
• The AXI Bridge IP core translates the AXI4 memory read or writes to PCI-Express Transaction Layer Packets and translates PCIe memory read and write requests to AXI4 transactions.
• All interfaces support fully parallel operation without any interferences. Interfaces that are not required can be turned off individually and do not occupy logic resources.

• The High Channel Count (HCC) DMA IP core for PCI-Express is a powerful PCIe Endpoint with multiple industry standard AXI Interfaces.
• This IP addresses continuous streaming applications from up to 64 different data sources. Each channel is able to transmit data into a separate memory area.
• Up to 16 AXI Stream masters read DMA Data from the host and present it to the user logic. Additional 8 AXI4 masters are available to interface full AXI or AXI-Lite peripherals with the host.

• AXI standard interfaces for easy integration
• User transmits/receives only user data without PCIe protocol
• All AXI Interfaces have adjustable Datawidth and separate clocking

This Universal NOR Flash IP supports a variety of NOR Devices and multiple Protocols, combines ease of use with high reliability, low power and speed under all conditions, including automotive applications.

The xSPI master IP supports the xSPI JESD251 standard from a standard AXI4 slave interface, and also features backwards compatibility support for Octal SPI, QSPI, DSPI, and SPI interfaces. Also supports JEDEC SFDP Standard.

• The xSPI/PSRAM master IP is easy to use, simple to work with, quick to operate, and reliable under all conditions.  It supports the xSPI JESD~251 standard from a standard AXI3 or AXI4 slave interface. 
• It also supports APMemory Octal/QSPI RAM, HyperRAM, HyperFlash, and features backwards compatibility support for Octal SPI, QSPI, DSPI, and SPI interfaces.

• The QSPI master core is easy to use, simple to work with, quick to operate, and reliable under all conditions.
• It supports the majority of QSPI devices standard from a standard AXI4 slave interface. It also features support for Octal SPI, Dual SPI (DSPI), and SPI interface.

• The xSPI PHY is designed to work with both the xSPI/PSRAM and the xSPI master host controller IPs. When coupled with the ACS xSPI PHY, the combined IPs are able to interact with SPI, Dual SPI, Quad SPI, Octal SPI, and xSPI devices at the full 200 MHz data rate.
• This includes both HyperRAM and HyperFlash protocols. Both single and dual data rate modes are supported. The xSPI Master controller IP supports flash devices, whereas the xSPI/PSRAM controller has been designed to support SRAM types of devices using the same interface.

• The ULL PCIe DMA Controller is a high-performance, bidirectional data transfer solution. It is designed for seamless communication between FPGAs and host CPUs over PCIe.
• With a round-trip time as low as 585ns*, this IP core empowers developers to maximize resource utilization and achieve ultra-low latency without compromising performance.