Peripheral IP
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979
Peripheral IP
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SPI to AHB Bridge
- The SPI to AHB bridge is an SPI slave that provides a link between a SPI bus (that consists of two data signals, one clock signal and one select signal) and AMBA AHB.
- On the SPI bus the slave acts as an SPI memory device where accesses to the slave are translated to AMBA accesses.
- The core can translate SPI accesses to AMBA byte, half-word or word accesses. The access size to use is configurable via the SPI bus.
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SPI Controller
- The SPICTRL provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus.
- Through registers mapped into APB address space the core can be configured to work either as a master or a slave.
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10/100 Mbit Ethernet MAC
- The GRETH core implements a 10/100 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface.
- The core implements the 802.3-2002 Ethernet standard. Receive and transmit data is autonomously transferred between the Ethernet MAC and the AMBA AHB bus using DMA transfers.
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CAN 2.0 Controller with DMA
- GRCAN is a CAN 2.0 IP core that implements an internal CAN controller and an AHB DMA backend.
- The APB bus is used for configuration, control and status handling and the AHB bus is used for retrieving and storing CAN messages via the DMA engine.
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FPGA Scrubber Controller
- GRSCRUB is an FPGA supervisor responsible for programming and scrubbing the FPGA configuration memory to prevent the accumulation of radiation-induced errors.
- The GRSCRUB IP currently supports the AMD/Xilinx Kintex UltraScale and Virtex-5 FPGA families.
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SpaceWire link controller with SpaceWire RMAP support and AMBA host interface
- Full implementation of Spacewire standard
- Protocol ID extension ECSS-E-50-12 part 2
- Optional RMAP protocol draft C
- AMBA AHB back-end with DMA
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PowerPC Bus Arbiter
- Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
- Designed for ASIC or PLD implementations in various system environments.
- Fully static design with edge triggered flip-flops.
- Supports up to eight PowerPC bus masters with unlimited slave device support.
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PowerPC to PCI Bridge
- Fully supports PCI specification 2.1 and 2.2 protocol.
- Designed for ASIC and PLD implementations.
- Fully static design with edge triggered flip-flops.
- Supports all PowerPC CPU with 603 bus interface and MPC860 interface.
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PowerPC Bus Slave
- Fully supports PowerPC 60x bus protocol including PowerPC 603, 604, 740, 750 and MPC8260.
- Designed for ASIC or PLD implementations in various system environ-ments.
- Fully static design with edge triggered flip-flops.
- Direct support for standard asynchronous SRAM and synchronous BURST SRAM.
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PowerPC Bus Master
- Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
- Designed for ASIC or PLD implementations in various system environments.
- Fully static design with edge triggered flip-flops.
- Automatic bus arbitration for address bus and data bus based on internal bus request.