Peripheral IP

The SONY_CAM_IF IP Core provides a simple way to connect the Sony® FCB-EV range of cameras to your FPGA.
It serves as a direct replacement for an external LVDS receiver IC and takes advantage of the fast LVDS I/O solutions provided by modern FPGA devices.

The SPI_SLAVE IP Core is an SPI compliant slave interface controller. The controller decodes the bus signals and de-serializes them into a series of 8-bit bytes.
Communication with the slave controller is achieved by programming a single control register and a single address register.

The CODEC_8B10B IP Core is a scalable 8B/10B Encoder/Decoder pair suitable for a wide range of serial data transmission applications.
The design is optimized for very high-speed operation and is suitable for use in serial data links of 6 GHz+ on basic FPGA devices.

The AC97-CTRL Audio Controller is a configurable IP block designed to simplify the integration of the AC'97 audio interface into ASIC and FPGA designs.
Fully compliant with the Intel Audio Codec '97 (AC’97) Revision 2.3 specification, this controller facilitates reliable transmission and reception of stereo or multi-channel audio streams using the well-established AC-Link interface.
With support for a single codec operating at a standard 48 kHz sample rate, the core is ideal for embedded applications that demand proven audio infrastructure with a compact silicon footprint and efficient data handling.

CVI is a fully Customizable Video Input controller IP core.
The video input controller can be applied to e.g. FPGA systems with a resource optimized, application specific feature configuration or to ASIC projects applying a more generic feature set and thus more flexibility.

CDC is a fully Customizable Display Controller IP supporting up to 16k resolutions (4096x4096 pixel) on a MIPI-DPI compliant parallel video output.
Several features can be configured at synthesis time and programmed at run time.
The display controller can be applied to e.g. FPGA systems with a resource optimized, application specific feature configuration or to ASIC projects applying a more generic feature set and thus more flexibility.

A2R provides an interconnection mechanism between control registers in an ASIC design and any number of control devices; CPUs, debug ports etc..
The bus is especially suited for synthesizable designs. It is specifically developed to meet the challenges of long interconnect delays in large System-on-chip designs and can be tailored to match system clock rates.

A2B is a high performance System-on-Chip interconnect designed for use in synthesizable designs.
It is specifically developed to meet the challenges of multiprocessor and multiple DMA / IO processor designs.
A2B is designed to have the highest possible occupancy so that the sustainable bus bandwidth closely approaches the available peak bandwidth of a given configuration.

The MC-SDMA IP core implements a highly configurable, bandwidth-efficient, and easy-to-use Direct Memory Access (DMA) controller that transfers data between the host system’s memory and multiple peripherals equipped with streaming interfaces.
The core interfaces with the host memory via a manager AMBA^® AXI4 (memory-mapped) port and provides access to its configuration and status registers (CSRs) via a subordinate AXI4-Lite or APB4 interface.

The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, which interfaces the host system with an AXI4 Memory-Mapped master port and the peripheral with either a slave or a master AXI4-Stream port.
The core operates in either Scatter-Gather (SG) Mode, reading descriptors from a run-time defined memory mapped-location, or in Direct Mode, transferring data according to a descriptor stored in local registers.