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Search (1,431)
Compare 1,431 Peripheral IP from 108 vendors (1 - 10)
  • xSPI - PSRAM Master
    • SPI Protocol:
    • AXI4 Slave
    • AXI4 DMA Master
    • AXI4 – LITE SLAVE
    Block Diagram -- xSPI - PSRAM Master
  • ONFI 5.0 PHY
    • The PHY design supports the newly introduced NV-LPDDR4 mode along with SDR, NV_DDR, and NV_DDR2, NV_DDR3 mode.
    Block Diagram -- ONFI 5.0 PHY
  • xSPI NOR Flash controller
    • Memory mapped access to the connected flash devices
    • Continuous Burst transfer support
    • Auto boot support
    Block Diagram -- xSPI NOR Flash controller
  • I3C Host Controller
    • Compliant with MIPI I3C Specification V1.0
    • Supports up to 12.5 MHz operation using Push-Pull.
    Block Diagram -- I3C Host Controller
  • ONFI Flash Controller
    • AXI System Interface
    • NAND Flash
    Block Diagram -- ONFI Flash Controller
  • Tessent Bus Monitor
    • Full transaction and trace-level visibility of on-chip bus traffic
    • Wide range of measurements, analytics statistics: Transactions, Bus cycles, latency, duration, beats, bus concurrency
    • Supports AXI, ACE, ACE-lite
    • Run-time configurable
    Block Diagram -- Tessent Bus Monitor
  • PCIe 5.0 Controller with AXI
    • Comprises complete PCIe 5.0 interface subsystem with Rambus PCIe 5.0 PHY
    • Supports the PCI Express 5.0 rev. 1.0 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s) and PIPE (8, 16, 32 and 64-bit) specifications
    • Supports the PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
    • Supports Endpoint, Root-Port, Dual-mode configurations
    Block Diagram -- PCIe 5.0 Controller with AXI
  • ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
    • Page Size – 2KB, 4KB, 8KB, 16KB
    • Bank/chip select options
    • Programmable timing
    Block Diagram -- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 16nm
  • PCIe 4.0 Controller with AXI
    • Internal data path size automatically scales up or down (64-, 256- bits) based on link max. speed and width for reduced gate count and optimal throughput
    • Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs up to Gen4 x8/Gen3 x16 with same RTL code
    • Stringent implementation of PCIe to AXI Ordering Rules and AXI to PCIe Ordering Rules guarantees AXI deadlock prevention
    • Carefully engineered AXI bridge & AXI interconnect allows full performance on AXI interfaces
    Block Diagram -- PCIe 4.0 Controller with AXI
  • ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
    • Page Size – 2KB, 4KB, 8KB, 16KB
    • Bank/chip select options
    • Programmable timing
    Block Diagram -- ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
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