Peripheral IP

Compare 931 Peripheral IP from 85 vendors (1 - 10)

Verification IP for Arm AMBA ACE Protocol
- Complete protocol support for AMBA ACE 5, H, J and K, ACE4, ACE-Lite, AXI5, AXI4, AXI4-Lite, and AXI3.
- Configurable interconnect model for AXI5, AXI4, AXI, ACE5, and ACE4
- Backdoor access to ACE primary cache
Verification IP for AMBA AHB
- Complete protocol support for AHB5, AHB3, AHB2, AHB-Lite, and AHB Multi Layer
- Includes primary, secondary, monitor
- Configurable bus model
- Backdoor access to AHB secondary memory
Verification IP for AMBA APB
- Native SystemVerilog/Verilog with UVM
- Includes primary, secondary, monitor
- Runs natively on all major simulators
- Built-in UVM sequence library
Verification IP for Arm AMBA CHI Protocol
- AMBA 5 CHI-A/B/C/D/E/F/G
- Request node, secondary node agents and monitor
- Complete port-level checks
- Supports all interface types
Verification IP for AMBA AXI
- Complete protocol support for AXI5, AXI-J/K, AXI4, AXI4-Lite, AXI3
- Programmable number of Managers, Subordinates, and Port Monitors
- Interconnect model
- System Monitor
Verification IP for AMBA ATB
- Trace Data Transfer (Valid, ready signaling)
- Narrow Trace Data Transfer (Data Valid Bytes signaling)
- Flow Control (Valid, ready signaling)
- Flush Request Response (Flush Valid, Ready signaling with Data transfer)
Verification IP for AMBA AXI4-Stream
- Native SystemVerilog/Verilog with UVM
- Runs natively on all major simulators
- Reference Verification Platform
- Built-in verification plan and coverage
Simulation VIP for AMBA CHI
- Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
- Generates constrained-random bus traffic with predefined error injection
- Callbacks access at multiple queue points for scoreboarding and data manipulation
- Provides comprehensive checking and coverage model
Simulation VIP for AMBA CHI-C2C
- Incorporating the latest protocol updates, the Cadence Verification IP for CHI-C2C provides a complete bus functional model (BFM), integrated automatic protocol checks, and a coverage model.
- Designed for easy integration in testbenches at IP, systems with multiple CPUs, accelerators, or other device chiplets, the VIP for CHI-C2C provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms.
eSPI LPC Bridge IIP
- Compliant with version 1.1 LPC Interface Specifications and eSPI base specification as defined in Enhanced Serial Peripheral Interface (eSPI) Specification rev.1.0
- Converts eSPI Peripheral Channel Transactions into LPC Memory write or read instructions
- Supports full LPC host capability
- Supports SOC Slave

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