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USB 3.1 Cable Marker IP
- USB PD 3.1 compliant.
- Single chip solution – just two external capacitors.
- 4 pin package.
- Less than 1mm2 area in 180nm.
- PROM programmed through vendor message protocol.
- Based on Obsidian’s mature PD technology.
- Integrated PROM enables customized response to a wide range of vendor requirements.
- Active Ra pulls down only requires 10uA at 5V., but is <1K below 2V.
- Power <5mW. Enabled by CC data activity. I.e. very low duty cycle.
- Programming can be done after assembly into the cable. Fuse lock function.
- Supports low cost, 4 layer PCB assembly.
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eFPGA IP - 100% third party standard cells
- Every element of the eFPGA can be defined in numbers: logic cells, adaptive DSP (with and without FIR engine, add & mult size, amount), RAM (type and amount) and IOs.
- In addition, Menta eFPGA IP Cores being 100% standard cells based, multiple power / performances trade-off can be achieved based on customer requirements.
- The eFPGA IP Cores are provided as hard IPs (GDSII).
- Menta eFPGA IP Cores use standard cells, and as such integrate smoothly into any standard ASIC design flow. Designers use RTL as the input to our software Origami Programmer to generate the eFPGA program file (bitstream) and obtain accurate performance evaluation.
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Complete USB Type-C Power Delivery IP
- Mixed signal Analog Front End Macros for 65n, 130n, 150nm, and 180n technologies.
- RTL code from AFE to I2C compatible register set.
- Stand alone C code for Protocol, Device Policy Manager, and System Policy Manager.
- IP demonstration & development board, with compliance reports.
- Full chip integration of USB Type-C, and associated software.
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High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
- Fractional-N digital PLL architecture, using an LC-tank oscillator
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Low Voltage, Low Power Fractional-N PLLs
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
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General Purpose Fractional-N PLLs
- Low power, suitable for logic clocking applications
- Extremely small die area, using a ring oscillator
- Twelve bits fractional resolution
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Fractional-N PLLs for Performance Computing
- Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 4GHz
- Reference clock from 10MHz to 500MHz
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24-bit Cap-less ADC 106 dB SNR
- I2C and APB control interface
- Embedded low noise voltage regulator for best resilience to power supply noise
- Low BoM and capacitor-less input connection
- High dynamic range for high quality recording in far-field applications
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24-bit Cap-less ADC 106 dB SNR low power and low latency 3 channels
- I2C and APB control interface
- Embedded low noise voltage regulator for best resilience to power supply noise
- Low BoM and capacitor-less input connection
- High dynamic range for high quality recording in far-field applications
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Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
- Low noise: high power Supply Rejection Ratio (PSRR): - 65 dB at F < 10 kHz
- Low intrinsic noise: 20 uVRMS at 10 Hz to 20 kHz
- Low Bill-of-Material: optimized in density for the best trade-off for the given output current and input voltage range
- Cost efficient solution compared to external Power Management.
