IP for SMIC

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Compare 1,092 IP for SMIC from 39 vendors (1 - 10)
  • NFC-V tag IP supporting ISO15693-3
    • The 180SMIC_NFCV_01 is a tag IC that works with NFCV technology.
    • When connected to an antenna designed according to the IC parameters, the tag is able to accumulate energy and exchange information with the reader.
    • The IC is compliant with is ISO/IEC 15693-3 standard and NFC Forum NFC-V.
    Block Diagram -- NFC-V tag IP supporting ISO15693-3
  • NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
    • The IP block provides the physical layer implementation of ISO 14443 interface. In particular, it includes the necessary functional devices for receiving data on the connected antenna, for the response load modulation, received and transmitted data (de)framing and parallel interface to external CPU.
    • This IP also can be used for adding NFC functionality to mobile devices and other applications to perform high-level RFID protocol tasks.
    Block Diagram -- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
  • NFC wireless interface supporting ISO14443 A and B on SMIC 180nm
    • The IP block provides the physical layer implementation of ISO 14443 interface. In particular, it includes the necessary functional devices for receiving data on the connected antenna, for the response load modulation, received and transmitted data (de)framing and parallel interface to external CPU.
    • This IP also can be used for adding NFC functionality to mobile devices and other applications to perform high-level RFID protocol tasks.
    Block Diagram -- NFC wireless interface supporting ISO14443 A and B on SMIC 180nm
  • UHF RFID tag IP with 512bit EEPROM and -19dBm sensitivity
    • 180SMIC_RFID_EPCGen2_01 IP is intended for use in passive UHF transponder applications.
    • IP derives its operating power from an RF electromagnetic field generated by a reader, which is received and rectified by the IP.
    • The IP tag sends the answer back to the reader using a backscatter modulation technique.
    Block Diagram -- UHF RFID tag IP with 512bit EEPROM and -19dBm sensitivity
  • Crystal Oscillators
    • The crystal oscillator macros are available in a wide range of industry-standard quartz crystals and MEMS resonators operating in the fundamental mode in the 32 kHz to 80 MHz range.
    • These oscillators, which are both power and area efficient, have a programmable transconductance to allow users to find the optimal balance between jitter and power consumption.
    Block Diagram -- Crystal Oscillators
  • Free running oscillators
    • Compact and low power
    • No external components
    • Baseline CMOS logic process masks only
    • Excellent frequency precision over PVT after trimming
    Block Diagram -- Free running oscillators
  • LVDS Deserializer IP
    • The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
    • Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.
    Block Diagram -- LVDS Deserializer IP
  • LVDS Serializer IP
    • The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels.
    • The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components.
    Block Diagram -- LVDS Serializer IP
  • 4.25 Gbps Multi-Standard SerDes
    • The MXL4254A is a silicon proven Quad Gigabit SerDes implemented in digital CMOS technology. Each of the four channels supports data rate up to 4.25 Gbps.It is compatible with router-backplane links, PCI Express, SATA, RapidIO, 10 Gbps Ethernet (XAUI), FibreChannel, SFI-5, SPI-5, and other communication applications.
    Block Diagram -- 4.25 Gbps Multi-Standard SerDes
  • MIPI D-PHY IP
    • The D-PHY is partitioned into a Digital Module – CIL (Control and Interface Logic) and a Mixed Signal Module. It is provided as a combination of Soft IP views (RTL, and STA Constraints) for Digital Module, and Hard IP views (GDSII/CDL/LEF/LIB) for the Mixed Signal Module.
    • This unique offering of Soft and Hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow.
    Block Diagram -- MIPI D-PHY IP
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