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Compare 1,160 IP for SMIC from 40 vendors (1 - 10)
  • eFPGA IP - 100% third party standard cells
    • Every element of the eFPGA can be defined in numbers: logic cells, adaptive DSP (with and without FIR engine, add & mult size, amount), RAM (type and amount) and IOs.
    • In addition, Menta eFPGA IP Cores being 100% standard cells based, multiple power / performances trade-off can be achieved based on customer requirements.
    • The eFPGA IP Cores are provided as hard IPs (GDSII).
    • Menta eFPGA IP Cores use standard cells, and as such integrate smoothly into any standard ASIC design flow. Designers use RTL as the input to our software Origami Programmer to generate the eFPGA program file (bitstream) and obtain accurate performance evaluation.
    Block Diagram -- eFPGA IP - 100% third party standard cells
  • Complete USB Type-C Power Delivery PHY, RTL, and Software
    • USB PD 3.1 compliant.
    • 8 bit register interface for a low speed processor, or optional I2C interface.
    • Integrated Chapter 6 protocol reduces required MPU response time to 10mS.
    Block Diagram -- Complete USB Type-C Power Delivery PHY, RTL, and Software
  • Bi-Directional LVDS with LVCMOS
    • TIA/EIA644A LVDS and sub-LVDS compatibility
    • Receiver also compatible with LVPECL
    • Operates over 2Gbps and up to 3Gb/s in some processes
    • Trimmable on-die termination, can be enabled while Tx is operating for better signal integrity
    Block Diagram -- Bi-Directional LVDS with LVCMOS
  • Fractional-N Frequency Synthesizer PLL
    • Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
    • Input & output frequency ranges greater than 1000:1
    Block Diagram -- Fractional-N Frequency Synthesizer PLL
  • High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
    • Fractional-N digital PLL architecture, using an LC-tank oscillator
    Block Diagram -- High Performance Fractional-N RF Frequency Synthesizer PLLs for 5G, WiFi, etc
  • Low Voltage, Low Power Fractional-N PLLs
    • Low power, suitable for IoT applications
    • Good jitter, suitable for clocking digital logic.
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
    Block Diagram -- Low Voltage, Low Power Fractional-N PLLs
  • General Purpose Fractional-N PLLs
    • Low power, suitable for logic clocking applications
    • Extremely small die area, using a ring oscillator
    • Twelve bits fractional resolution
    Block Diagram -- General Purpose Fractional-N PLLs
  • Fractional-N PLLs for Performance Computing
    • Low jitter, suitable for many clocking applications, including high speed digital, ADC, DAC, medium-speed PHY
    • Extremely small die area (< 0.005 sq mm), using a ring oscillator
    • Output frequency can be from 1 to 400 times the input reference, up to 4GHz
    • Reference clock from 10MHz to 500MHz
    Block Diagram -- Fractional-N PLLs for Performance Computing
  • 24-bit Cap-less ADC 106 dB SNR
    • I2C and APB control interface
    • Embedded low noise voltage regulator for best resilience to power supply noise
    • Low BoM and capacitor-less input connection
    • High dynamic range for high quality recording in far-field applications
    Block Diagram -- 24-bit Cap-less ADC 106 dB SNR
  • 24-bit Cap-less ADC 106 dB SNR low power and low latency 3 channels
    • I2C and APB control interface
    • Embedded low noise voltage regulator for best resilience to power supply noise
    • Low BoM and capacitor-less input connection
    • High dynamic range for high quality recording in far-field applications
    Block Diagram -- 24-bit Cap-less ADC 106 dB SNR low power and low latency 3 channels
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