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SpaceWire link controller with SpaceWire RMAP support and AMBA host interface
- Full implementation of Spacewire standard
- Protocol ID extension ECSS-E-50-12 part 2
- Optional RMAP protocol draft C
- AMBA AHB back-end with DMA
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SpaceFibre and WizardLink Interface
- SpaceFibre codec designed according to the SpaceFibre specification ECSS-E-ST-50-11C, single-lane implementation
- WizardLink codec designed to interface with Texas Instrument TLK2711 transceiver
- The IP can inter-operate with off-chip SerDes devices or with FPGA/ASIC hard macros
- Optional 8b10b encoding
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Infiniband 4X Link Protocol Engine
- The Link Protocol Engine (LPE) is single core solution incorporating in Link Layer of Open System Interconnect (OSI) which significantly reduces the time and cost of implementing complex InfiniBand target system designs.
- InfiniBand is an open architecture interconnect solution to handle and resolve bottleneck of multiple I/O streams simultaneously.
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Intel® Precision Time Protocol Servo (Intel® PTP Servo) FPGA IP
- Coordinate the actions of disparate electronic systems that must be synchronized in time with Intel® PTP Servo, which employs hardware timestamping of packets and can achieve sub-microsecond accuracy to address the needs of synchronization requirements across various applications.
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Serial Lite II Intel® FPGA IP Core
- The Serial Lite II Intel® FPGA IP core provides a simple and lightweight way to move data from one point to another reliably at high speeds
- It consists of a serial link of up to 16 bonded lanes with logic to provide a number of basic and optional link support functions
- The Atlantic* interface is the primary access for delivering and receiving data.
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Serial Lite IV Intel® FPGA IP Core
- The Serial Lite IV Intel® FPGA Intellectual Property (IP) core is suitable for high-bandwidth data communication for chip-to-chip, board-to-board, and backplane applications.
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LVDS Tunneling Protocol and Interface (LTPI) IP
- LVDS Tunneling Protocol and Interface (LTPI) is a soft IP introduced in the DC-SCM 2.0 Specification to facilitate the tunneling of low-speed signals between the host platform module (HPM) and secure control module (SCM) through the low-voltage differential signaling (LVDS) interfaces.
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ARINC 429 IP Core
- ARINC 429 IP Core implements ARINC 429 standard.
- IP Core contains Rx and Tx processing blocks, Controller Block, Internal Memory and External Memory Interfaces.
- A429 IP communicates with CPU (Central Processing Unit) and external memory through AXI interface.
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ARINC 664 (AFDX) End System DO-254 IP Core
- The ARINC 664 (AFDX) End System DO-254 IP Core (AFDX ES IP) implements an AFDX End System as specified in ARINC 664 Part 7 “Avionics Full-Duplex Switched Ethernet (AFDX) Network”.
- The AFDX ES IP supports MII, RMII, GMII or SGMII as PHY interfaces. Therefore, it is able to transmit and receive at 10 Mbps, 100 Mbps or 1000 Mbps, making full usage of the bandwidth.
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ARINC 429 Transmitter DO-254 IP Core
- The ARINC 429 Tx IP Core implements a transmitter as specified in the ARINC Specification 429 Part 1-17.
- The ARINC 429 Rx Core has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit.
