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Compare 81 Other from 31 vendors (1 - 10)
  • LPC Verification IP
    • The LPC Verification IP provides an effective & efficient way to verify the LPC components of an IP or SoC.
    • The LPC VIP is fully compliant with LPC Specification version 1.1
    • The VIP is lightweight with easy plug-and-play components so that there is no hit on the design cycle time.
    Block Diagram -- LPC Verification IP
  • LPC Assertion IP
    • Compliant to LPC 1.1 specifications.
    • Supports bandwidth upto 33 MHz.
    • Supports the following operations
    Block Diagram -- LPC Assertion IP
  • eSPI LPC Bridge IIP
    • Compliant with version 1.1 LPC Interface Specifications and eSPI base specification as defined in Enhanced Serial Peripheral Interface (eSPI) Specification rev.1.0
    • Converts eSPI Peripheral Channel Transactions into LPC Memory write or read instructions
    • Supports full LPC host capability
    • Supports SOC Slave
    Block Diagram -- eSPI LPC Bridge IIP
  • LPC Device IIP
    • Compliant with version 1.1 LPC Specification.
    • Full LPC Device/Peripheral functionality
    • Supports the following operations:
    • Memory read and write
    Block Diagram -- LPC Device IIP
  • LPC Host IIP
    • Compliant with version 1.1 LPC Specifications.
    • Full LPC Host functionality.
    • Supports the following operations:
    • Memory read and write
    Block Diagram -- LPC Host IIP
  • LPC Synthesizable Transactor
    • Compliant to LPC 1.1 specifications.
    • Supports bandwidth up to 33 MHz.
    • Supports the following operations
    • Memory read and write
    Block Diagram -- LPC Synthesizable Transactor
  • LPC Verification IP
    • Compliant to LPC 1.1 specifications.
    • Supports bandwidth up to 33 MHz.
    • Supports the following operations.
    • Memory read and write
    Block Diagram -- LPC Verification IP
  • PMBus Verification IP
    • Fully compliant with Rev. 1.4 of the PMBus Specification.
    • Support for all SMBus protocols with and without PEC (Packet Error Checking).
    • Support for SMBus ARP (Address Resolution Protocol) for dynamically assigning a unique address to each slave device.
    • Support Group command protocol for multiple PMBus device communication.
    Block Diagram -- PMBus Verification IP
  • RTC Verification IP
    • Compliant to RTC basic specification as defined in DS3234 maxim_spi_rtc
    • Supports configurable timing parameters and multi-slave configurations.
    • Supports multi-slave memory.
    • Supports Master and Slave Mode.
    Block Diagram -- RTC Verification IP
  • SMBus Verification IP
    • Fully compliant with Rev. 3.1 of the SMBus Specification
    • Support PEC (Packet error Checking) for communication robustness.
    • Support for all Bus protocols with and without PEC.
    • Support for SMBus ARP (Address Resolution Protocol) for dynamically assigning a unique address to each slave device.
    Block Diagram -- SMBus Verification IP
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