IP Catalog > Interface IP Cores > Other

Other

All offers in Other
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (72)
Compare 72 Other from 34 vendors (1 - 10)
  • Ethercat Synthesizable Transactor
    • Supports ETG.1000 S(R) V1.0.3 specification
    • Supports Low Voltage Differential signaling interface
    • Supports MII, MDIO RMII and RGMII Interface as per the ISO/IEC 8802-3 specification
    • Supports RMII and RGMII Interface
    Block Diagram -- Ethercat Synthesizable Transactor
  • ASA Verification IP
    • Adherent to ASA Specification version 1.01, 1.1 and 2.0.
    • Support both Downstream and Upstream Mode of communication
    • Supports 5 fixed-rate Speed Grades ranging from 2 Gbps to 16 Gbps in Downstream direction
    • Supports 2 fixed-rate Speed Grades ranging from 2 Gbps to 4 Gbps in Upstream direction
    Block Diagram -- ASA Verification IP
  • SENT Verification IP
    • Adherent to Single Edge Nibble Transmission (SENT) SAE J2716.
    • Supports Both Slow and Fast Channel Transmission
    • Supports Following Types of Frames for SLOW channel Transmission
      • Short Serial Message Format
      • Enhanced Serial Message Format
    • Short Serial Message Format
    Block Diagram -- SENT Verification IP
  • ARM HSSTP PHY with Link Layer
    • ARM HS-STP v6.0
    • ARM Coresight DDI 0314H
    • Xilinx Aurora 8b/10b v2.2
    Block Diagram -- ARM HSSTP PHY with Link Layer
  • LVDS TX and RX PHY
    • The LVDS implements LVDS TIA/EIA protocol, providing a low-voltage, high-speed point-to-point signal interface
    • It supports either DDR-type (sensor-side) or Byte-type (screen-side)
    • It uses differential signaling to transmit data over a constant-impedance transmission line, ensuring robust noise immunity and low power consumption
    Block Diagram -- LVDS TX and RX PHY
  • ARINC 664 (AFDX) End System DO-254 IP Core
    • The ARINC 664 (AFDX) End System DO-254 IP Core (AFDX ES IP) implements an AFDX End System as specified in ARINC 664 Part 7 “Avionics Full-Duplex Switched Ethernet (AFDX) Network”.
    • The AFDX ES IP supports MII, RMII, GMII or SGMII as PHY interfaces. Therefore, it is able to transmit and receive at 10 Mbps, 100 Mbps or 1000 Mbps, making full usage of the bandwidth.
    Block Diagram -- ARINC 664 (AFDX) End System DO-254 IP Core
  • SENT/SAE J2716 Controller
    • The CSENT core implements a controller for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and is capable of driving pulses to trigger synchronous Sensor type.
    • It can be used for conveying data from one or multiple sensors to a centralized controller using a single SENT line.
    Block Diagram -- SENT/SAE J2716 Controller
  • Simulation VIP for SMBus
    • SMBus Devices
    • Controller target, or host
    • Packet Error Checking
    • Performs PEC on transmit and receive data on applicable packets
    Block Diagram -- Simulation VIP for SMBus
  • IPSec Verification IP
    • Provides Ethernet fully compliant to 802.3-2018 supporting all media independent interfaces for (1/10/25/40/50/100/200/400/800 G)
    • Provides IPSec as per RFC-4301 specification
      • Supports Tunnel Mode and Transport Mode
      • Supports Authentication header (AH)
      • Supports Encapsulating Security Payload (ESP)
      • Supports Manual as well as automatic Key Exchange
      • Encodes and decodes Ip headers
      • Protects and validates ipSec using AES-GCM Cipher suites
      • Cryptographic protection
    • Supports Tunnel Mode and Transport Mode
    • Supports Authentication header (AH)
    Block Diagram -- IPSec Verification IP
  • LTTPR Verification IP
    • Supports 8b/10b encoding and 128/132b encoding.
    • LTTPR is compliant with DP1.4, DP2.0, and DP2.1.
    • DisplayPort VIP Supports Singe as well as Multi LTTPR environment.
    • LTTPR supports FEC encoding and decoding.
    Block Diagram -- LTTPR Verification IP
×
Semiconductor IP