Arithmetic Mathematic IP

ATAN2_XY calculates the 4-quadrant inverse tangent in the range -π to π. It has a fully pipelined architecture and uses fixed-point mathematics throughout.
Input values are accepted as 12-bit signed numbers in the range -2048 to 2047.
The calculated output phase (in radians) is a 19-bit signed value with 1 sign bit, 2 integer bits and 16 fractional bits.

ATAN_X calculates the inverse tangent of a fraction. It has a fully pipelined architecture and uses fixed-point mathematics throughout.
Input values are accepted as 16-bit unsigned fractions in the range 0 to 1. Output values are 16-bit unsigned fractions in the range 0 to π/4.
Both input and output values are in [16 16] format with 0 integer bits and 16 fraction bits.

High-speed fully pipelined 32-bit floating-point square-root function based on the IEEE 754 standard. Features a generic latency from 2 to 24 clock cycles.
Ideal for floating-point pipelines, arithmetic units and processors.

High-speed fully pipelined 32-bit floating-point divider based on the IEEE 754 standard.
Features a generic latency from 2 to 49 clock cycles.
Ideal for floating-point pipelines, arithmetic units and processors.

The A2FD is a fully synthesizable module implemented in Verilog RTL.
It is a co-processor unit providing floating-point computation compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic (IEEE Standard).
It is designed to provide high performance floating-point computation while minimizing die size and power. Pipelined, single-cycle throughput operation is available for all operations except Divide, Remainder and Square Root operations.

The A2FM product is a collection of floating-point execution units compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic (IEEE-754 Standard).
The units are designed for high frequency, high throughput implementations. Each unit is implemented as a state less pipeline that can easily be integrated into a high-performance processor design.

The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
A parameter defines the ratio of the input width to the output width.
For example, if the input width is 32-bits and the Reduction Factor is 4 the the output width is 8-bits.

The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
A parameter defines the ratio of the input width to the output width.
For example, if the input width is 8-bits and the Expansion Factor is 4 the the output width is 32-bits.

The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
The interface is fully compatible with a Standard FIFO interface and they may be mixed and matched.
A “Stall” may be generated by gating the POP and ORDY signals to arrest the normal flow of data down the pipeline and allows any given stage to take multiple cycles when necessary.

The A2FH is a co-processor unit providing floating-point computation compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic (IEEE-754R Standard).
It is designed to provide a powerful floating-point functionality for low-power, low frequency applications.