I2C IP

Compare 120 I2C IP from 29 vendors (1 - 10)

1.2V/3.3V GPIO Library with 3.3V I2C ODIO in TSMC 110nm
- A TSMC 110nm Wirebond and Flipchip compatible I/O library with 1.2V/3.3V Fail-Safe GPIO, 3.3V I2C Open-Drain I/O, SPI and associated ESD.
- This silicon proven, wirebond and flipchip compatible library is particularly tailored to address gaps in the native foundry IO offerings for this node.
- It features a 1.2V/3.3V GPIO with selectable drive strengths and optional internal 100K ohm pull up or pull down resistor and a selectable Schmitt trigger.
MIPI-I3C Master (SDR) RTL Design IP
- MIPI I3C master Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs)
- The MIPI I3C master Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system The MIPI I3C master Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus
MIPI I3C Controller Host/Target IP
- MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs)
- The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system
APB I2C Master/Slave Controller
- The I2C Interface provides full support for the two-wire I2C synchronous serial interface, compatible with the ACCESS.
- Bus physical layer, with additional support for the SMBus protocol, including Packet Error Checking (PEC).
- Through its I2C compatibility, it provides a simple interface to a wide range of low-cost memories and I/O devices, including: EEPROMs, SRAMs, timers, A/D converters, D/A converters, clock chips, and peripheral drivers.
I2S - Ensures proper audio data transmission, synchronization, and integrity
- I2S (Inter-IC Sound) is a serial bus interface used for connecting digital audio devices. As a Verification IP (VIP), it ensures proper data transmission, signal integrity, timing, and protocol compliance in audio communication systems.
- This VIP verifies key elements such as word length, frame synchronization, clock behavior, and error handling, making it essential for testing I2S communication in a range of applications, including consumer electronics, automotive, and medical devices
I2C - Verifies I2C communication, ensuring protocol compliance and error-free data transfer
- I2C (Inter-Integrated Circuit) is a low-speed communication protocol designed for embedded systems. As a Verification IP (VIP), it simulates and validates I2C interfaces, ensuring accurate data transmission, addressing, and error handling.
- This VIP supports various device roles, data rates, and stress-testing scenarios, such as clock stretching and multi-master configurations, ensuring reliable communication in applications like sensor interfacing and memory device validation
I3C Controller IP – I3C / I2C Slave, SCL Clock only, Configure User Registers, no CPU Host Required
- The DB-I3C-S-SCL-CLK-REG is an I3C Slave Controller IP Core focused on low power, low noise, low VLSI footprint ASIC / ASSP designs requiring the configuration & control of registers with no free running clock.
- The DB-I3C-S-SCL-CLK-REG processes the I3C protocol & physical layers, and receives & transmits bytes with respect to the I3C payload to / from User Registers within an ASIC / ASSP / FPGA device.
- The DB-I3C-S-SCL-CLK-REG Controller implements the Slave-Transmit and Slave-Receive protocol according to the MIPI I3C-Basic-Spec-ver1_0 specification.
I3C Controller IP – I3C / I2C Slave, Configure User Registers, no CPU Host Required
- The DB-I3C-S-REG is an I3C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs requiring the configuration & control of registers with no local host processor.
- The DB-I3C-S-REG processes the I3C protocol & physical layers, and receives & transmits bytes with respect to the I3C payload to / from User Registers within an ASIC / ASSP / FPGA device.
- The DB-I3C-S-REG Controller implements the Slave-Transmit and Slave-Receive protocol according to the MIPI I3C-Basic-Spec ver1_0 specification.
I2C Controller IP- Master / Slave, Parameterized FIFO, Avalon Bus
- The DB-I2C-MS-AVLN Controller IP Core interfaces a microprocessor via the Avalon Bus to an I2C Bus in Standard-Mode (100 Kbit/s) / Fast-Mode (400 Kbit/s) / Fast-Mode Plus (1 Mbit/s) / Hs-Mode (3.4+ Mb/s) / Ultra Fast-Mode (5 mbit/s).
- The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.
- The DB-I2C-MS-AVLN is a Master / Slave I2C Controller that in Master Mode controls the Transmit or Receive of data to or from slave I2C devices while in Slave Mode allows an external I2C Master device to control the Transmit or Receive of data.
I2C/SMBus Controller IP – Master / Slave, Parameterized FIFO, AXI/AHB/APB/Avalon Buses, SMBus Protocol
- The DB-I2C-SMBus-MS-AMBA Controller IP Core is an I2C/SMBus Master/Slave Controller, interfacing a microprocessor via the AMBA AXI, AHB, or APB Bus to an I2C/SMBus Interconnect. Both I2C and SMBus protocols are supported.
- The System Management Bus (SMBus) is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant SMBus devices, typically with a microprocessor behind the master controller and one or more slave devices.