IP Catalog > Chiplet and D2D IP

Chiplet and D2D IP

Chiplet and D2D (Die-to-Die) IP cores enable the integration of multiple chips or dies into a single system for improved performance, scalability, and efficiency. These IP cores facilitate seamless communication between individual chips, optimizing interconnects and reducing latency. Bunch of Wires IP ensures high-bandwidth, reliable connections between chips, while UCIe IP (Universal Chiplet Interconnect Express) provides a standardized interface for connecting chiplets, enabling flexible and modular chip designs. Additionally, Ultralink IP offers high-speed, low-latency communication for die-to-die interfaces, ensuring efficient data transfer across multiple processing units.

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Search (85)
Compare 85 Chiplet and D2D IP from 19 vendors (1 - 10)
  • UCIe Controller baseline for Streaming Protocols
    • Low latency controller for UCIe-based multi-die designs
    • Includes Die-to-Die Adapter layer and Protocol layer
    • Supports on-chip interconnect fabrics including AXI, CHI C2C, CXS, PCIe, CXL, and streaming
    • Error detection and correction with optional CRC and retry functionality
    Block Diagram -- UCIe Controller baseline for Streaming Protocols
  • Die-to-Memory (D2M) PHY
    • Unlike fixed unidirectional die-to-die solutions, NuLink technology is able to deliver low-power and high-performance D2M solutions.
    Block Diagram -- Die-to-Memory (D2M) PHY
  • Die-to-Die PHY
    • The NuLink technology delivers low-power and high-performance D2D IP core products, which support multiple industry standards and are available on both standard and advanced packaging.
    Block Diagram -- Die-to-Die PHY
  • 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
    • High Bandwidth Density and Data Rates
    • Package Configurability
    • Energy Efficiency
    • Fully Integrated Solution
    Block Diagram -- 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
  • UCIe Chiplet PHY & Controller
    • Compliant with the UCIe specification (2.0 & 1.1)
    • Flexible Structure, easy to customize (Pre-hardened PHY tuned to Customer Spec, PHY + Adapter Layer, PHY + Adapter Layer + Customized Protocol Layer)
    • Supports the CXS/AXI using the streaming package (AXI Interface bandwidth up to 89%)
    Block Diagram -- UCIe Chiplet PHY & Controller
  • <4Gbps Low Power D2D Interface in TSMC 16nm & 28nm
    • A <4Gbps, Wide I/O Compatible, Die to Die Interface in TSMC 16nm and 28nm.
    • This silicon proven die to die interface includes IP in both TSMC 16nm FFC/FFC+ and 28nm HPM/HPC/HPC+.
    • The I/O cells for both versions of the library are defined as TX only and RX only.
    Block Diagram -- <4Gbps Low Power D2D Interface in TSMC 16nm & 28nm
  • Low Power D2D Interface in TSMC 16nm FFC/FFC+
    • This library is a production-quality, silicon-proven custom Die-to-Die high speed interface available in TSMC’s 16nm process.
    • The I/O cell is bidirectional, has two modes of operation: standard full rail to rail swing, or a custom low noise pseudo-differential interface.
    • The RX cells have a weak pull-down feature.
    Block Diagram -- Low Power D2D Interface in TSMC 16nm FFC/FFC+
  • Universal Chiplet Interconnect Express(UCIe) VIP
    • The UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of your UCIe designs
    • The UCIe VIP is fully compliant with UCIe Specification version 1.0 and supports all the layers of the UCIe stack, such as FDI, RDI, LogPHY, PCIe, and CXL protocols
    • The UCIe VIP is also very user-friendly and flexible, with simple APIs, easy integrations, and configurable parameters
    Block Diagram -- Universal Chiplet Interconnect Express(UCIe) VIP
  • The UCIe CONTROLLER IP
    • The UCIe IP solution includes D2D Adapter layer which supports streaming/PCIe/CXL/Raw flitformats, supports both standard and advanced mainband links and sideband links
    Block Diagram -- The UCIe CONTROLLER IP
  • UCLe - Ensures reliable validation and efficient connectivity for chiplets
    • UCIe VIP is a state-of-the-art solution for validating and ensuring compliance in multi-chip semiconductor systems. With features like high-speed data transfer, protocol compliance, and advanced debugging, it guarantees robust and efficient chiplet communication.
    • This technology powers diverse applications, including HPC, AI/ML, automotive electronics, and telecommunications. It ensures seamless data flow, reliability, and energy efficiency across industries like edge computing, cloud platforms, and consumer electronics
    Block Diagram -- UCLe - Ensures reliable validation and efficient connectivity for chiplets
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