Input/Output Controller IP
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18
Input/Output Controller IP
from 15 vendors
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10)
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xSPI - PSRAM Master
- The xSPI/PSRAM master IP is easy to use, simple to work with, quick to operate, and reliable under all conditions. It supports the xSPI JESD~251 standard from a standard AXI3 or AXI4 slave interface.
- It also supports APMemory Octal/QSPI RAM, HyperRAM, HyperFlash, and features backwards compatibility support for Octal SPI, QSPI, DSPI, and SPI interfaces.
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QSPI Master IP
- The QSPI master core is easy to use, simple to work with, quick to operate, and reliable under all conditions.
- It supports the majority of QSPI devices standard from a standard AXI4 slave interface. It also features support for Octal SPI, Dual SPI (DSPI), and SPI interface.
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SDIO/SD Memory/MMC Slave Controller
- Compatible with SD/SDIO specification 2.0 with 1 and 4 bit data transfer.
- Provides SD interface to peripheral or memory device through a simple address/data interface.
- Support SD, SPI and optional MMC bus protocol.
- Support for both standard capacity and high capacity (SDHC) memory cards.
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General Purpose Input / Output Controller (GPIO)
- The GPIOmodule is a general purpose input/output controller, offering some unique features that eases system integration and use.
- Each GPIO port can be configured for input, output or bypass mode. Output data can be set in one access or single or multiples bits can be set or cleared.
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APB General Purpose IO (w/ interrupt)
- The APB GPIO is a configurable module allowing the use of up to 32 scalable I/O lines.
- If more than 32 I/Os are required, more than one GPIO module may be instantiated.
- Each line can be configured independently resulting in a very useful I/O application.
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Intel 8255A Functional Equivalent Programmable Peripheral Interface
- The DB8255A Programmable Peripheral Interface core is a full function equivalent to the Intel 8255A / 82C55A and Intersil 82C55A devices.
- The DB8255A implements a general-purpose I/O interface connecting peripheral equipment to a microprocessor system bus.
- The core generates 24 programmable I/O lines which are individually programmed in 2 groups of 12 and used in 3 major modes of operation.
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General-Purpose I/O Controller with APB Interface
- User selectable number of GPIO signals from 1 to 32
- All GPIO signals can be bi-directional (external bi-directional I/O cells are required in that case)
- All GPIO signals can be tri-stated or open-drain enabled (external tri-state or open-drain I/O cells are required in that case)
- GPIO signals programmed as inputs can cause an interrupt request to the CPU
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I3C Master and Slave Dual Role Controller
- Compliant with the latest version of the MIPI I3C specification
- Legacy I2C
- I3C features
- Low Power
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APB4 General Purpose Input/Output Module
- Compliant with AMBA APB v2.0 Specification
- User-defined number of Bi-directional General Purpose IO
- Automatic synchronisation of General Inputs to Bus Clock
- Each General Output configurable as push-pull or open-drain
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PS/2 Keyboard controller, fully configurable
- PS/2 core is used to communicate with either keyboard or mouse device
- PS/2 core can be configured to use single or dual connection signals within the same core
- AHB or WISHBONE SoC Interconnection Rev B compliant interface
- PS/2 can operate in pooling or interrupt mode