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Input/Output Controller IP

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Compare 30 Input/Output Controller IP from 15 vendors (1 - 10)
  • APB General Purpose IO (w/ interrupt)
    • The APB GPIO is a configurable module allowing the use of up to 32 scalable I/O lines.
    • If more than 32 I/Os are required, more than one GPIO module may be instantiated.
    • Each line can be configured independently resulting in a very useful I/O application.
    Block Diagram -- APB General Purpose IO (w/ interrupt)
  • Intel 8255A Functional Equivalent Programmable Peripheral Interface
    • The DB8255A Programmable Peripheral Interface core is a full function equivalent to the Intel 8255A / 82C55A and Intersil 82C55A devices.
    • The DB8255A implements a general-purpose I/O interface connecting peripheral equipment to a microprocessor system bus.
    • The core generates 24 programmable I/O lines which are individually programmed in 2 groups of 12 and used in 3 major modes of operation.
    Block Diagram -- Intel 8255A Functional Equivalent Programmable Peripheral Interface
  • General-Purpose I/O Controller with APB Interface
    • User selectable number of GPIO signals from 1 to 32
    • All GPIO signals can be bi-directional (external bi-directional I/O cells are required in that case)
    • All GPIO signals can be tri-stated or open-drain enabled (external tri-state or open-drain I/O cells are required in that case)
    • GPIO signals programmed as inputs can cause an interrupt request to the CPU
    Block Diagram -- General-Purpose I/O Controller with APB Interface
  • I3C Dual Controller
    • Compliant with MIPI I3C Specification (v1.1/v1.1.1)
    • Compliant with MIPI I3C HCI Specification (v1.2)
    • Supports up to 12.5 MHz operation using Push-Pull
    • Open-Drain and Push-pull type transactions
    Block Diagram -- I3C Dual Controller
  • xSPI - PSRAM Master
    • SPI Protocol:
    • AXI4 Slave
    • AXI4 DMA Master
    • AXI4 – LITE SLAVE
    Block Diagram -- xSPI - PSRAM Master
  • Quad SPI Master IP
    • Compliant with AMBA AXI3/4 and AXI4-lite protocols.
    • User configurable clock frequency support
    • Designed to support all leading NOR FLASH devices.
    Block Diagram -- Quad SPI Master IP
  • xSPI Master IP | NOR IP
    • JESD 251 compliant
    • JEDEC SFDP Compliant
    Block Diagram -- xSPI Master IP | NOR IP
  • I3C Master and Slave Dual Role Controller
    • Compliant with the latest version of the MIPI I3C specification
    • Legacy I2C
    • I3C features
    • Low Power
    Block Diagram -- I3C Master and Slave Dual Role Controller
  • APB4 General Purpose Input/Output Module
    • Compliant with AMBA APB v2.0 Specification
    • User-defined number of Bi-directional General Purpose IO
    • Automatic synchronisation of General Inputs to Bus Clock
    • Each General Output configurable as push-pull or open-drain
    Block Diagram -- APB4 General Purpose Input/Output Module
  • I3C Slave Controller
    • Compliant with MIPI I3C Specification V1.0
    • Supports up to 12.5 MHz operation using Push-Pull.
    Block Diagram -- I3C Slave Controller
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