Vision Processor IP
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27
Vision Processor IP
from 11 vendors
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10)
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NPU IP for Embedded AI
- Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
- Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
- Future proof architecture that supports the most advanced ML data types and operators
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IP cores for ultra-low power AI-enabled devices
- Ultra-fast Response Time
- Zero-latency Switching
- Low Power
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NPU IP family for generative and classic AI with highest power efficiency, scalable and future proof
- Support wide range of activations & weights data types, from 32-bit Floating Point down to 2-bit Binary Neural Networks (BNN)
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Single channel ADAS chip with FuSa monitor
- The SFA 250A has been designed to be easy to adapt to suit the support needs of the customer’s IP as it is scalable, both in terms of function and performance, as well as modular as multiple versions can be combined to form larger solutions.
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Quad channel ADAS IP platform
- Can cut design cost and time to market by up to 30%.
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High Number of Streams Decoder For Data Center
Enables up to 256 streams decoding with robustness, high throughput single-core solution, or multi-core solution, supporting VVC, AV1, HEVC, H.264, AVS3, AVS2, VP9 video formats, JPEG, and legacy formats.
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High Number of Streams Encoder For Data Center
- Enables up to 256 streams encoding with high video quality single-core solution, or multi-core solution, supporting AV1, HEVC, H.264, VP9 video formats and JPEG.
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Video Decoder Processor IP
- Unified architecture supports multiple formats
- VVC main profile 8/10bit
- AV1 main profile 8/10bit
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High Image Quality Super Resolution IP
- Up to 8K @ 60 FPS
- Up to 4 pixels per clock
- FLEXA PSI interface in streaming mode or AXI interface in memory-to-memory mode
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Comprehensive, High Throughput Pixel Operation IP
- PC820 IP offers a rich array of foundational video and image processing capabilities, facilitating seamless integration with major video and graphics processing IPs, AI processors, and data pathways of the Host CPU.