ADC / DAC IP

The IP consists of an 8 bit current steering DAC clocked externally for 4 - 6 GS/s. The differential output signal of maximum +/- 800 mV is driven onto a load impedance of 100 Ohm and can be calibrated within a range of +/- 25 % of its nominal value to adjust to load conditions.
The IP needs an external clock with high accuracy and low periodic jitter, because the clock jitter influences the dynamic behavior of the converter.

The ADC IP is a general-purpose successive approximation converter for low-power medium resolution applications. Sample rate, resolution and power consumption are configurable.
It is built using typical differential capacitor-DAC architecture, clocked comparator and bootstrapped switches. No additional reference voltage is required, achieving lmost rail-to-rail input. The target applications are environmental and biomedical signal processing.

This pipelined ADC can be applied for up to 20MSps sampling frequencies. By using interleaved switched-capacitor circuitries a CLK signal with half the sampling rate needs to be applied.
This ADC is built as a single-ended architecture and is designed to convert input signals from 0.5 – 2.3V at 3.3V supply voltage with up to 10 MHz input bandwidth with 12 bits resolution.

This fully differential ADC is designed to convert full swing (-1V to +1 V) input signals as well as unipolar input signals (0V to + 1V), each with 16 bits resolution.
Low-frequency noise reduction is provided using chopper-modulation.
The embedded power down mode provides a linear relation between power consumption and conversion rate of the ADC.

The IP consists of a Successive Approximation Register (SAR) architecture ADC using charge-redistribution technique.
The ADC IP is configurable regarding resolution (6-13 bit) and sample rate (up to 10kS/s) and power consumption down to 1.9 µW. The input voltage range is quasi-rail-to-rail guaranteeing more than + 1.7 V@ 1.8V power supply.
An optional calibration technique can be applied to compensate degraded mismatch behavior of technology capacitors.

The ADC IP is a general-purpose sigma-delta converter and it is configurable for conversion speed and power consumption with adaptable oversampling ratio.
It is built using typical second order architecture using correlated-double-sampling method. The target application is sampling of transient input voltages with 8k S/s with low-power and 192 kS/s respectively.

This cyclic ADC, based on redundant-signed-digit (RSD) conversion, is optimized for power efficiency and high accuracy. It provides 12 bit resolution for sampling frequencies up to 54 kS/s for continuous input signals.
This single ended ADC is designed to convert input signals with input swing of 1.9 V. The resolution is configurable (12 bit, 16 bit). Reference voltages can be generated on-chip or applied from outside.