ADC / DAC IP

Most of the signals directly encountered in science and engineering are continuous: light intensity that changes with distance; voltage that varies over time; a chemical reaction rate that depends on temperature, etc. ADC IPs (Analog-to-Digital Converter) and DAC IPs (Digital-to-Analog Converter) are the IP cores that allow digital designs to interact with these everyday signals.

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Compare 739 ADC / DAC IP from 63 vendors (1 - 10)
  • 12-bit/16-bit SAR ADC
    • 12 bits 100Msps SAR ADC on 28nm process; 
    • 12 bits 25Msps SAR ADC and Pipeline ADC above 100Msps on 40/55nm process; 
    • 16 bits 2/1Msps SAR ADC on 40/55nm process;
    Block Diagram -- 12-bit/16-bit SAR ADC
  • 12-bit 400MSPS ADC on TSMC 7nm
    • The ODT-ADS-12B2400M-7T is an ultra low power ADC designed for use in a 6/7nm CMOS process.
    • This 12-bit, 400MSPS ADC supports input signals up to 200MHz and features a differential full-scale range of 1.0Vpp and excellent static and dynamic performance.
    Block Diagram -- 12-bit 400MSPS ADC on TSMC 7nm
  • 10-bit 2.5GSPS ADC
    • The ODT-ADS-10B2P5G-T16 is an ultra lowpower, high-performance time-interleaved ADC designed in a 16nm CMOS process.
    • This 10-bit, 2.5GSPS ADC supports input signals up to 1.0 GHz and features a differential full-scale range of 1.0Vpp with excellent static and dynamic performance.
    Block Diagram -- 10-bit 2.5GSPS ADC
  • 12 bit, 200 MSPS ADC on TSMC 16nm FFC
    • The ODT-ADS-12B200M-16FFCT is an ultra low power ADC designed in a 16nm CMOS process.
    • This 12-bit, 200MSPS ADC supports input signals up to 100MHz and features a differential full-scale range of 1.0Vpp and excellent static and dynamic performance.
    Block Diagram -- 12 bit, 200 MSPS ADC on TSMC 16nm FFC
  • 16-bit 5MSPS DAC on TSMC 16 FFC
    • The ODT-DAC-16B5M-SV-T16 is an ultra-low power, voltage output, 16-bit DAC with a high performance, class AB output buffer.
    • The DAC uses a proprietary architecture that guarantees monotonicity. It also features low glitch, low drift, small area and low power consumption.
    • VSENSE pin is provided to set the load voltage with high accuracy. Both VOUT and VSENSE pins must be routed to the load.
    Block Diagram -- 16-bit 5MSPS DAC	on TSMC 16 FFC
  • 12-bit, 2 GSPS High Performance RF DAC in 12nm CMOS
    • The ODT-DAC-12B2G-12 is a high-performance current steering 12-bit DAC that operates at an update rate of up to 2GSPS.
    • The DAC uses a proprietary architecture that reduces harmonic and intermodulation distortions at high output frequency and amplitudes.
    • The high-performance DAC supports 20mA (maximum) differential output current and achieves up to -149dBm/Hz noise spectral density with excellent SFDR.
    Block Diagram -- 12-bit, 2 GSPS High Performance RF DAC in 12nm CMOS
  • 12-bit, 5 MSPS ADC with 8:1 Input Mux in a TSMC 6nm
    • The ODT-ADS-12B5M-6T is an ultra-low-power, high-linearity ADC with rail-to-rail inputs designed in a TSMC 6nm process.
    • This 12-bit, 5MSPS ADC supports input signals up to 1 MHz and features excellent static and dynamic performance.
    • The input front-end includes a mux that can support 16 single-ended or differential inputs.
    Block Diagram -- 12-bit, 5 MSPS ADC with 8:1 Input Mux in a TSMC 6nm
  • 12-bit, 4 GSPS High Performance IQ ADC in GF22FDX
    • GF22FDX Process
    • 12-bit resolution, 4GSPS update rate
    • Dual ADC configured as IQ Pair
    Block Diagram -- 12-bit, 4 GSPS High Performance IQ ADC in GF22FDX
  • 12-bit, 8 GSPS ADC in 7nm CMOS
    • The ODT-ADS-12B8G-7nm is an ultra-highperformance time-interleaved ADC designed in a 7nm CMOS process.
    • This 12-bit, 8GSPS ADC supports input signals up to 2.5 GHz and features a differential fullscale range of 0.8Vpp and excellent static and dynamic performance.
    Block Diagram -- 12-bit, 8 GSPS ADC in 7nm CMOS
  • 12 bit, 500 MSPS ADC on GF 22FDX
    • The ODT-ADS-12B500M-G22FDX is an ultra-low power ADC designed in a 22nm CMOS process.
    • This 12-bit, 500MSPS ADC supports input signals up to 100MHz and features a differential full-scale range of 0.8Vpp and excellent static and dynamic performance.
    • The ADC architecture is optimized to maximize performance while minimizing power and area consumption. The ADC includes an integrated input buffer.
    Block Diagram -- 12 bit, 500 MSPS ADC on GF 22FDX
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