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ADC / DAC IP

Most of the signals directly encountered in science and engineering are continuous: light intensity that changes with distance; voltage that varies over time; a chemical reaction rate that depends on temperature, etc. ADC IPs (Analog-to-Digital Converter) and DAC IPs (Digital-to-Analog Converter) are the IP cores that allow digital designs to interact with these everyday signals.

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Search (752)
Compare 752 ADC / DAC IP from 66 vendors (1 - 10)
  • Pipeline ADC
    • High Sampling Rate: Capable of sampling up to 125 million samples per second, suitable for high-speed applications
    • 8-bit Resolution: Provides 8-bit digital output, delivering precise quantization of input signals
    • Pipeline Architecture: Ensures low latency and high throughput, ideal for real-time processing
    • Low Power Consumption: Optimized for minimal power usage, enhancing energy efficiency in portable and battery-powered devices
    Block Diagram -- Pipeline ADC
  • Sigma-Delta ADC
    • Dynamic Range: 100 dB
    • Resolution: High-resolution digital output
    • Sigma-Delta Modulation: Advanced noise shaping and low distortion
    • Power Consumption: Optimized for low power, typically in the milliwatt range
    Block Diagram -- Sigma-Delta ADC
  • SAR ADC
    • High Sampling Rate: Capable of sampling up to 640 million samples per second, making it suitable for ultra-high-speed applications
    • 12-bit Resolution: Delivers 12-bit digital output, providing superior precision and accuracy in signal quantization
    • SAR Architecture: Ensures high speed and low latency with excellent power efficiency
    • Ultra-Low Power Consumption: Optimized for minimal power usage, ideal for energy-sensitive applications
    Block Diagram -- SAR ADC
  • 40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
    • Rail-to-Rail IQ ADC Input Capability
    • 65dB IQ ADC SNR
    • Programmable Full-Scale IQ DAC Output Current
    • 65dB IQ DAC SNR
    Block Diagram -- 40nm 1.1V AFE comprising 12-bit IQ ADC, 12-bit IQ DAC and Clock-PLL
  • 12-bit 40nm 1.1V 320MHz Digitally-Assisted IQ Current DAC
    • Programmable Full-Scale Output Current
    • Dual (I and Q) Channels
    • Scalable Power Consumption
    • Configurable Randomiser Algorithms
    Block Diagram -- 12-bit 40nm 1.1V 320MHz Digitally-Assisted IQ Current DAC
  • 12-bit 40nm 1.1V 320MHz Digitally-Assisted Current DAC
    • Programmable Full-Scale Output Current
    • Scalable Power Consumption
    • Configurable Randomiser Algorithms
    • Return-to-Zero Mode
    Block Diagram -- 12-bit 40nm 1.1V 320MHz Digitally-Assisted Current DAC
  • 180nm 13-bit Sigma-Delta ADC
    • 1.8V low-power 32MHz single-bit switched-capacitor SD Modulator-based 7.8125kHz-to-62.5kHz-Nyquist-rate ADC with programmable Decimation Rate
    Block Diagram -- 180nm 13-bit Sigma-Delta ADC
  • 12-bit 40nm 1.1V 64MHz-to-340MHz continuous-time Delta-Sigma ADC
    • Integrated Dual-Channel Continuous-time Delta-Sigma Modulator (I + Q)
    • Integrated Dual decimate-by-8 Cascaded-Integrator-Comb Decimation Filter
    Block Diagram -- 12-bit 40nm 1.1V 64MHz-to-340MHz continuous-time Delta-Sigma ADC
  • 12-bit 40nm 1.1V 80MHz Asynchronous-SAR IQ ADC
    • Rail-to-Rail Input Capability
    • Dual (I and Q) Channels
    • Scalable Power Consumption
    • No need for external high-speed SAR clock
    Block Diagram -- 12-bit 40nm 1.1V 80MHz Asynchronous-SAR IQ ADC
  • 12-bit 40nm 1.1V 80MHz Asynchronous-SAR ADC
    • The TRV101TSM40LP IP is a 1.1V low-power low-silicon-area 12-bit 80MHz Asynchronous-SAR ADC implemented in TSMC Low-Power 40nm CMOS process technology.
    • Its 40MHz Nyquist bandwidth makes it especially suitable for use in carrier-aggregated wireless communication integrated circuit subsystems (LTE, WiFi, WiMAX etc).
    Block Diagram -- 12-bit 40nm 1.1V 80MHz Asynchronous-SAR ADC
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