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MIPI IP

MIPI IP cores enable seamless communication between processors, sensors, and peripherals in mobile, automotive, and consumer electronics applications. Two key components of MIPI IP cores are the MIPI Controller IP and MIPI PHY IP. The MIPI Controller IP manages the data transfer process, ensuring efficient and reliable communication between devices, while the MIPI PHY IP handles the physical layer of the interface, ensuring high-speed, noise-resistant signal transmission.

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Search (695)
Compare 695 MIPI IP from 49 vendors (1 - 10)
  • SLIMbus Host IP V2.0
    • The MIPI SLIMbus Host v2.0 typically resides in a mobile platform’s application processor and provides two-wire, multipurpose connectivity with multiple audio and another low/mid bandwidth peripheral devices.
    • The SLIMbus Host Controller IP is designed to provide MIPI SLIMbus 2.0 compliant connectivity to an SoC.
    Block Diagram -- SLIMbus Host IP V2.0
  • SLIMbus Device IP Core
    • The SLIMbus v2.0 Device Controller IP is designed to provide MIPI SLIMbus compliant connectivity for a peripheral device, like an audio codec, to a SLIMbus compliant host, like an Applications Processor on a mobile platform, and share the bus bandwidth with other SLIMbus devices that may exist.
    Block Diagram -- SLIMbus Device IP Core
  • RFFE Slave IP Core
    • Compliant with MIPI’s RFFE specification Rev 3.0
    • Small silicon footprint
    • Scalable Implementation
    • Up to 15 Devices can be connected per Bus
    • Low pin count on Interface side (SCLK and SDATA)
    Block Diagram -- RFFE Slave IP Core
  • RFFE Master IP Core
    • Compliant with MIPI RFFE Specification 3.0
    • Delivered in Reuse Methodology Manual (RMM) compliant Verilog RTL format
    • Optionally delivered as a physical design
    • Small footprint
    Block Diagram -- RFFE Master IP Core
  • MIPI UniPro Software Stack
    • The MIPI Alliance was created to define and promote open standards for interfaces to mobile application processors. The UniPro (Unified Protocol) is one in a family of standard addressing the mobile market. UniPro is a high speed interface technology for interconnecting integrated circuits in mobile phones or compatible products. The targeted scenario for UniPro technology is to connect chips (such as application processor to a peripheral device) within a mobile terminal.
    • The Arasan UniPro software stack serves as a path for applications to transmit data over the hardware stack and also to indicate the availability of data from the remote host. The stack exports a generic set of device operation APIs (such as initialization, configuration, data transfer, callback registration for event notifications, shutdown etc.) for easy integration with client applications. It provides an easy-to-use interface to client application by managing all the nitty-gritty details of UniPro protocol in the stack itself. A layered architecture for the stack makes it possible to port, configure and expand to various platforms, OS and various target hardware devices.
    • The UniPro software stack implements a scheduling engine and connection specific input output queue to provide better memory utilization and to provide Quality of Service (QoS) for different requirements of the stream. Hardware does the physical bus arbitration and scheduling of packets for TC0 and TC1 traffic classes at physical level. The software does the scheduling mapping at more granular reason based on requirements of a stream.
    Block Diagram -- MIPI UniPro Software Stack
  • MIPI SoundWire Slave Controller 1.2
    • MIPI SoundWire®Slave Controller, typically integrated into audio DSP/Codecs or directly into audio peripherals such as Microphones and Amplifiers used in smart phones, tablets and mobile PCs. 
    • The IP when integrated provides SoundWire, a new audio interface to connect to Master typically embedded in Application Processor or Audio Codecs.
    Block Diagram -- MIPI SoundWire Slave Controller 1.2
  • MIPI SoundWire Master Controller 1.2
    • Compliant with MIPI SoundWire specification version 1.2
    • Configurable number of Data Ports Configurable Direction – Source or Sink
    • Implements clock gearbox with programmable frequency divider
    • Implements SoundWire Bus Clock Stop and WakeUp detection
    Block Diagram -- MIPI SoundWire Master Controller 1.2
  • MIPI SLIMbus Software Stack
    • Compliant with MIPI SLIMbus® Specification version 1.01
    • Portability in choice of OS, processors and hardware
    • Easy-to-use interface for applications
    • Fully documented generic interface API
    Block Diagram -- MIPI SLIMbus Software Stack
  • MIPI SLIMbus Hardware Validation Platform
    • The SLIMbus® (Serial Low-power Inter-chip Media bus protocol) Hardware Validation Platform provides the mobile industry a versatile means to assist in the development and debugging of SLIMbus® products.
    • By emulating a real-world SLIMbus host component, this platform can be used by system and software developers to completely validate the implementation of the SLIMbus interface in their products during various stages of the development cycle.
    Block Diagram -- MIPI SLIMbus Hardware Validation Platform
  • MIPI M-PHY® 4.1 Analog Transceiver
    • The M-PHY is of Type 1, which apply to UFS, LLI, and CSI-3 protocols. The Multi-gear M-PHY 4.1 consists of analog transceivers, high-speed PLL, data recovery units as well as state-machine control — all in a single GDSII.
    • The interface to the link protocol-specific controller (host or device) is compliant with the M-PHY RMMI specification, which allows seamless integration of the two IPs, namely the controller and the PHY, into the chip design.
    Block Diagram -- MIPI M-PHY® 4.1 Analog Transceiver
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