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MIPI IP

MIPI IP cores enable seamless communication between processors, sensors, and peripherals in mobile, automotive, and consumer electronics applications. Two key components of MIPI IP cores are the MIPI Controller IP and MIPI PHY IP. The MIPI Controller IP manages the data transfer process, ensuring efficient and reliable communication between devices, while the MIPI PHY IP handles the physical layer of the interface, ensuring high-speed, noise-resistant signal transmission.

Explore our vast directory of MIPI IP cores below.

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Search (693)
Compare 693 MIPI IP from 51 vendors (1 - 10)
  • MIPI D-PHY - 28nm, 14nm, 8nm, 5nm, 4nm
    • The MIPI D-PHY IP is a hard-macro PHY for CSI RX and DSI TX. IO pads and EDS structures are included.
    • In addition, extensive built-in self-test features, such as loopback and scan, are supported.
    • It offers a cost-effective and low-power solution.
    Block Diagram -- MIPI D-PHY - 28nm, 14nm, 8nm, 5nm, 4nm
  • MIPI C-PHY - 28nm, 14nm, 8nm, 5nm, 4nm
    • The MIPI C-PHY IP is a hard-macro PHY for CSI RX. IO pads and ESD structures are included.
    • In addition, extensive built-in self-test features, such as loopback and scan, are supported.
    • It offers a cost-effective and low power solution.
    Block Diagram -- MIPI C-PHY - 28nm, 14nm, 8nm, 5nm, 4nm
  • MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY - 14nm, 8nm, 5nm, 4nm
    • The MIPI D-PHY/C-PHY Combo IP is a hard-macro PHY for CSI RX or DSI TX. IO pads and ESD structures are included.
    • In addition, extensive built-in self-test features, such as loopback and scan, are supported.
    • It offers a cost-effective and low-power solution.
    Block Diagram -- MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY - 14nm, 8nm, 5nm, 4nm
  • MIPI CSI-2 RX Controller
    • The CSI-2 RX controller IP is optimized for low power, small size and high-speed interfaces, supporting a wide range of higher image resolutions.
    • The CSI-2 RX Controller IP is fully compliant with the CSI-2 v2.0 specification and supports the DPHY v2.0 and CPHY v1.2.
    Block Diagram -- MIPI CSI-2 RX Controller
  • DSI-2 TX/RX Controller
    • The DSI-2 TX/RX controller IP is optimized for low power, small size and high-speed interfaces between an application processor and display modules using either MIPI CPHY or MIPI DPHY.
    • The DSI-2 TX/RX Controller IP is fully compliant with the DSI v1.3 specification and supports the DPHY
    Block Diagram -- DSI-2 TX/RX Controller
  • MIPI SWI3S Manager Core IP
    • The SWI3S (SoundWire I3S Interface) Manager Controller Core IP implements the link protocol to communicate in half-duplex fashion to transfer the Audio streams and the Control information together.
    • One or more SWI3S Peripheral IP can be connected specific to the application.
    Block Diagram -- MIPI SWI3S Manager Core IP
  • CSI-2 v2.1 Receiver IP
    •  Fully compliant to MIPI standard
    • Small footprint
    • Functionality ensured with comprehensive verification
    • Product quality proven with silicon
    Block Diagram -- CSI-2 v2.1 Receiver IP
  • MIPI I3C Target Device
    • MIPI I3C Basic Specification v1.2 compiliance
    • Native 32-bit CPU Interface
    • Optional CPU interface wrappers (APB, AHB, AXI)
    • Legacy I2C communication with 7-bit Static Address
    • I3C Single Data Rate (SDR) mode
    Block Diagram -- MIPI I3C Target Device
  • MIPI D-PHY TX PHY and DSI controller
    • Scalability and Flexibility: Supports multiple data lanes for higher aggregate bandwidth, any of the multiple lanes can be configured into Clock Lane
    • High Data Rates: Supports data transmission rates up to 4.5Gbps per lane, allowing for high-resolution displays and smooth refresh rates
    • Energy Efficiency: Optimized for low power consumption, making it ideal for battery-powered devices
    • Complete Solution: Combines the MIPI D-PHY Transmitter PHY and DSI Controller to make it a one-stop solution
    Block Diagram -- MIPI D-PHY TX PHY and DSI controller
  • Verification IP for I3C/I2C
    • A comprehensive memory VIP solution portfolio for I3C and I2C s used by system-on-chip (SoC) and IP designers to ensure comprehensive verification and protocol and timing compliance.
    • Avery Verification IP for Control/Serial Buses implements a complete set of models, protocol checkers and compliance testsuite in 100% native SystemVerilog and UVM.
    Block Diagram -- Verification IP for I3C/I2C
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