IP Catalog > Memory & Libraries IP

Memory & Libraries IP

Welcome to the ultimate Memory & Libraries IP hub! Explore our vast directory of Memory & Libraries IP.

Memory & Libraries IP cores include a large listing of memory compilers, non-volatile memory (NVM), logic libraries, and IO solutions.

All offers in Memory & Libraries IP
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (4,351)
Compare 4,351 Memory & Libraries IP from 92 vendors (1 - 10)
  • 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
    • A Flipchip I/O Library with dynamitcally switchable 1.8V/3.3V GPIO, 5V I2C/SM- Bus ODIO, 5V OTP Cell, 1.8V & 3.3V Analog Cells and associated ESD.
    • A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
    Block Diagram -- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
  • 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
    • A 1.8V/3.3V flip-chip I/O library with 4kV HBM ESD protection, I2C compliant ODIO and Hot-Plug Detect.
    • This library is a production-quality, silicon-proven I/O library in TSMC 16nm technology.
    • Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level.
    Block Diagram -- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
  • 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
    • A 1.8V/3.3V flip-chip I/O library with 4kV HBM ESD protection, I2C compliant ODIO and Hot-Plug Detect.
    • This library is a production-quality, silicon-proven I/O library in TSMC 12nm technology.
    • Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level.
    Block Diagram -- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
  • 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
    • A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V to 5V GPIO, 1.8V to 5V analog, with ultra low-cap/low-leakage RF solutions.
    • This silicon proven flip-chip compatible library in TSMC 180nm BCD features a multi-voltage GPIO, 1.8V to 5V analog I/O, and ultra-low capacitance and low leakage 36V+ ESD solutions. The library also includes 5V RF pads.
    Block Diagram -- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
  • 1.8V GPIO, 1.8V to 3.3V Analog in TSMC 180nm BCD
    • A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V GPIO, 1.8V to 3.3V Analog, with ultra low-cap/low-leakage 36V+ ESD solutions.
    • This silicon proven flip-chip compatible library in TSMC 180nm BCD features a 1.8V GPIO, 1.8 to 3.3V analog I/O, and ultralow capacitance and low leakage 36V+ ESD solutions.
    Block Diagram -- 1.8V GPIO, 1.8V to 3.3V Analog in TSMC 180nm BCD
  • 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
    • A TSMC 22nm Inline, Flip Chip compatible library with GPIO, ODIO, HDMI, LVDS, & Analog Cells.
    • This silicon-proven, flip chip compatible library in TSMC 22nm boasts a two speed GPIO: 75MHz and 150MHz.
    • The library also features a 5V ODIO. GPIO and ODIO cells have an orientation of NS and EW.
    Block Diagram -- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
  • Ultra-low leakage I/O Library in TSMC 22nm
    • A TSMC 22nm Wirebond I/O Library with ultra-low leakage 1.8V GPIO, 1.8V I2C ODIO, 1.8V analog cell and associated ESD.
    • This is an ultra-low leakage library. The GPIO has a typical leakage of only 150pA from VDDIO and 1nA from VDD.
    • The library has a GPIO and an ODIO. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or pull-down resistor.
    Block Diagram -- Ultra-low leakage I/O Library in TSMC 22nm
  • 0.9V/1.2V I/O Library in TSMC 55nm
    • A 0.9V/1.2V I/O Library in TSMC 55LP.
    • This SoundWire Digital I/O Library in TSMC 55nm LP offers an advanced, low-power interface solution for high-performance audio applications.
    • Supporting 0.9V/1.2V operation, this library provides Data, Clock, and Select I/Os, enabling seamless integration with SoundWire-based systems while delivering enhanced power efficiency.
    Block Diagram -- 0.9V/1.2V I/O Library in TSMC 55nm
  • 2Gbps LVDS/SVLS Combo Transceiver in TSMC 16nm
    • AD_SLVS_LVDS is a highly configurable 2Gbps transceiver for LVDS or SLVS interfaces. With features like dynamic interface selection, on-die termination and pre-emphasis, this I/O is flexible enough for any system.
    • To compliment this I/O, the vendor also offers a accompanying silicon-proven ESD and GPIO pad library in TSMC 12/16nm.
    • This I/O provides 2kV HBM protection but can be extended up to 8kV upon request.
    Block Diagram -- 2Gbps LVDS/SVLS Combo Transceiver in TSMC 16nm
  • LVDS Transceiver in TSMC 28nm
    • This 1.8V LVDS transceiver, designed for TSMCs 28nm process, delivers high-speed, low-power differential signaling with superior signal integrity.
    • Engineered with 1.8V thick oxide devices and a 0.8V standard core interface, it operates ef- ficiently across a wide temperature range (-40°C to 125°C).
    Block Diagram -- LVDS Transceiver in TSMC 28nm
×
Semiconductor IP