Memory & Libraries IP

The SD 3.0 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead.

The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.

The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels.
The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components.

The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI^® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard.
The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI).

The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI^® Alliance Standard for D-PHY and a high performance 4-channel LVDS Serializer implemented using digital CMOS technology.
In LVDS mode, both the serial and parallel data are organized into 4 channels. The parallel data is 7 bits wide per channel. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.

Library contains approx. 60 IO cells
Support for all metal-stacks of 22FDX®
Low voltage cells with nominal core voltages down to 0.4 V for glue-less interfacing to ULV Racyics® ABX digital standard cell domains
Low leakage cells for ultra low power always-on domain usage

Ultra-low voltage logic designs using adaptive body biasing demand dense SRAM solutions which fully integrate in the ABB aware implementation and sign-off flow of the Racyics® ABX Platform solution.
The Racyics® Single Rail SRAM supports ultra-low voltage operation down to 0.55 V where logic designs with Minimum-Energy-Point are implemented.

Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABB

Body biasing is a disruptive 22FDX® feature which enables the adaption of transistor threshold voltages after production during device operation.
Racyics® dense 9T logic standard cells libraries and low power 8T standard cell libraries are fully enabled for the adaptive body biasingaware implementation and sign-off flow of the Racyics® ABX® Platform solution.