Memory & Libraries IP

Compare 4,266 Memory & Libraries IP from 92 vendors (1 - 10)

ReRAM NVM in 130nm CMOS, S130
- Technology: 130nm, SkyWater S130
- Mask Adder: 2
- Supply Voltage: 1.8V Read, 1.8V+3.3/3.6V Program
Bi-Directional LVDS with LVCMOS
- TIA/EIA644A LVDS and sub-LVDS compatibility
- Receiver also compatible with LVPECL
- Operates over 2Gbps and up to 3Gb/s in some processes
- Trimmable on-die termination, can be enabled while Tx is operating for better signal integrity
Ultra High-Speed Cache Memory Compiler
- Up to 3.4 GHz operation in N3P process
- Cache size up to 16 Kb
- 4 – 64-bit word width
- Configurable way associativity
LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
- Compliant for JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
- x16 and x32 channel support
CodaCache® Last Level Cache IP
- Standalone IP
- 1.2 GHz frequency in 16FF+TT process
- Protocol interoperability: AMBA AXI 4
LVDS IO handling data rate up to 50Mbps with maximum loading 60pF
- Process: Silterra 0.16um CMOS 1P5M Process
- Supply Voltage Range: AVDD33 = 3.3v +/-10%, AVDD18 = 1.8v +/-10%
- Ambient Temperature: 0°C~80°C
- Compatible with BLVDS_25 of Spartan-3A FPGA
MIPI DPHY & LVDS Transmit Combo on GF55LPe
- MIPI D-PHY version 1.2 compliant PHY transmitter
- OpenLDI version 0.9 compliant LVDS transmitter
Next Generation Flash device enabling small size, low power and direct connection with digital circuit which opens up new possibiities
- small size
- low power
- direct connection with digital circuit
Embedded flash IP, 1.32V/3V 90nm
LPDDR5X/5/4X/4 combo PHY at 7nm
- Unbeatable performance-driven and low-power-driven PPA
- Ultra-low read/write latency with programmable PHY boundary timing
- Channel equalization with FFE and DFE