IP for UMC

Compare 3,042 IP for UMC from 46 vendors (1 - 10)

All Digital Fractional-N RF Frequency Synthesizer PLL in UMC 40LP
- Fractional Multiplication with frequencies up to 8GHz
- Extremely low jitter (< 300fs RMS)
- Small size (< 0.05 sq mm)
- Low Power (< 15mW)
All Digital Fractional-N PLL for Performance Computing in UMC 40LP
- Fractional multiplication with frequency up to 4GHz
- Low jitter (< 10ps RMS)
- Small size (< 0.01 sq mm)
- Low Power (< 5mW)
General Purpose All Digital Fractional-N PLL in UMC 40LP
- Low jitter (< 18ps RMS)
- Small size (< 0.01 sq mm)
- Low Power (< 3.5mW)
- Support for multi-PLL systems
USB Full Speed Transceiver
- Exceeds USB 2.0 Full Speed specification.
- Trimmed pull up resistor.
- Enable / suspend feature.
- DPF and UFP options available.
Crystal Oscillators
- The crystal oscillator macros are available in a wide range of industry-standard quartz crystals and MEMS resonators operating in the fundamental mode in the 32 kHz to 80 MHz range.
- These oscillators, which are both power and area efficient, have a programmable transconductance to allow users to find the optimal balance between jitter and power consumption.
Free running oscillators
- Compact and low power
- No external components
- Baseline CMOS logic process masks only
- Excellent frequency precision over PVT after trimming
LVDS Deserializer IP
- The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
- Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.
MIPI M-PHY IP
- The MIPI M-PHY is a high-frequency low-power, Physical Layer IP that supports the MIPI^® Alliance Standard for M-PHY.
- The IP can be used as a physical layer for many applications, connecting flash memory-based storage, cameras and RF subsystems, and for providing chip-to-chip inter-processor communications (IPC).
PowerPC Bus Arbiter
- Fully supports PowerPC 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
- Designed for ASIC or PLD implementations in various system environments.
- Fully static design with edge triggered flip-flops.
- Supports up to eight PowerPC bus masters with unlimited slave device support.
PowerPC to PCI Bridge
- Fully supports PCI specification 2.1 and 2.2 protocol.
- Designed for ASIC and PLD implementations.
- Fully static design with edge triggered flip-flops.
- Supports all PowerPC CPU with 603 bus interface and MPC860 interface.