IP for UMC
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3,139
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for UMC
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125Mbps to 16Gbps Multi-protocol SerDes PMA
- Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
- Extremely low jitter suitable for Enterprise SerDes applications
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250Mbps to 12.7Gbps Multiprotocol SerDes PMA
- Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
- Extremely low jitter suitable for Enterprise SerDes applications
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eFPGA IP - 100% third party standard cells
- Every element of the eFPGA can be defined in numbers: logic cells, adaptive DSP (with and without FIR engine, add & mult size, amount), RAM (type and amount) and IOs.
- In addition, Menta eFPGA IP Cores being 100% standard cells based, multiple power / performances trade-off can be achieved based on customer requirements.
- The eFPGA IP Cores are provided as hard IPs (GDSII).
- Menta eFPGA IP Cores use standard cells, and as such integrate smoothly into any standard ASIC design flow. Designers use RTL as the input to our software Origami Programmer to generate the eFPGA program file (bitstream) and obtain accurate performance evaluation.
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Complete USB Type-C Power Delivery PHY, RTL, and Software
- USB PD 3.1 compliant.
- 8 bit register interface for a low speed processor, or optional I2C interface.
- Integrated Chapter 6 protocol reduces required MPU response time to 10mS.
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Fractional-N Frequency Synthesizer PLL
- Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
- Input & output frequency ranges greater than 1000:1
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Quantum-Driven Hardware Root-of-Trust - Physical Unclonable Function (PUF)
- Scalability unlocked
- Secure root-of-trust
- No key injection
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Ultra low-power 2.4 GHz transceiver for Bluetooth Low Energy 5
- Voltage supply: 1.3V down to 1V, with graceful degradation down to 0.9V
- Compliant with direct operation from 1.2V battery
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MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
- Dual mode PHY can support C-PHY and D-PHY
- Supports MIPI Specification for D-PHY Version 1.2
- Supports MIPI Specification for C-PHY Version 1.0
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Dual 12-Bit 20 to 200MS/s 1.2V ADC, CMOS 90nm
- TSMC 90nm general purpose 1.2V CMOS process
- Single 1.2V supply
- 20 to 200 Mspls/s scalable sampling rate
- 0.5 Vp_diff input dynamic range
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PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
- Supports 2.5Gb/s serial data rate
- Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
- Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
- Data and clock recovery from serial stream on the PCI Express bus
