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Compare 129 Other from 26 vendors (1 - 10)
  • eMMC Host Controller IP
    • The eMMC Host controller IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
    • The eMMC 4.51 Host IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead.
    Block Diagram -- eMMC Host Controller IP
  • AMBA AHB Bus to SDRAM Controller
    • SDRAM controller interfaces directly with AHB Bus and user interface.
    • Built-in arbitration between two access ports.
    • Second access port allows memory sharing with user logic devices.
    • Dual write buffer for simultaneous write posting and SDRAM access.
    Block Diagram -- AMBA AHB Bus to SDRAM Controller
  • Pipeline SDRAM Controller
    • Designed with synthesizable HDL for ASIC and PLD synthesis.
    • Supports both discrete SDRAM chips and PC100/133 SDRAM DIMM.
    • Supports register mode and non-register mode SDRAM DIMM.
    • Supports industrial standard SDRAM from 64Mbit to 256Mbit device sizes.
    Block Diagram -- Pipeline SDRAM Controller
  • Synchronous ONFI NAND Flash Controller
    • Supports single-level and multi-level cells (SLC and MLC) NAND Flash devices.
    • Compatible with ONFI 2.1 Flash Interface for synchronous and asynchronous access.
    • Supports source synchronous double data rate data transfer for highest possible data bandwidth.
    • Supports 2k and 4k page sizes.
    Block Diagram -- Synchronous ONFI NAND Flash Controller
  • xSPI Multiple Bus Memory Controller
    • SLL’s unified xSPI Multiple Bus Memory Controller IP supports the widest range of JEDEC xSPI and xSPI-like NOR Flash and PSRAM memories (JEDEC xSPI Profile 1.0 and 2.0, HyperBus 1.0, 2.0 and 3.0, OctaBus and Xccela Bus) that are available now from many memory vendors.
    • JEDEC xSPI and xSPI-like memories offer good performance with lower hardware and power costs.  Memory device variants offer up to 512 Mbit PSRAM, up to 2 Gigabit NOR Flash, up to 250 MHz DDR clock speeds, with x4, x8 and x16 data path widths, and a wide range of package options including 4mm x 4mm BGA49 and tiny WLCSP footprints.  Some PRSAM devices are now also available with internal ECC.
    Block Diagram -- xSPI Multiple Bus Memory Controller
  • SDRAM Controller DO-254 IP Core
    • The SDRAM Controller implements a controller for Single Data Rate Synchronous Dynamic Random Access Memory (SDR SDRAM) devices as specified in the JEDEC Standard No. 21-C Page 3.11.5.1 Release 12.
    • Single Data Rate SDRAM can accept one command and transfer one word of data per clock cycle.
    Block Diagram -- SDRAM Controller DO-254 IP Core
  • xSPI NOR/NAND Flash & HyperRAM Controller
    • Memory mapped access to the connected flash devices
    • Continuous Burst transfer support
    • Auto boot support
    Block Diagram -- xSPI NOR/NAND Flash & HyperRAM Controller
  • Octal SPI DDR PSRAM controller
    • This controller supports AP Memory’s Xccela open standard Bus for digital interconnect and data communications, suitable for non-volatile and volatile memories such as PSRAM.
    • This controller enables smooth integration AP memory’s of Xccela PSRAM memory chips into various new-gen devices made with mobile and wearable low power SoCs’.
    • This memory controller implementation is designed to give the user full flexibility for driving the memory control signals and timing adjustment for data sampling.
    Block Diagram -- Octal SPI DDR PSRAM controller
  • Hyperbus Flash Memory Controller
    • Compatible with spansion hyperbus based memory products.
    • 0 Wait State Write Burst Operation for HyperBus memory on AXI interface of up to 256 words.
    Block Diagram -- Hyperbus Flash Memory Controller
  • AHB Internal SRAM Controller
    • AMBA® AHB Compatible
    • Handles byte, half, and word (8,16,32bit) accesses to internal SSRAM
    • Can be used with Internal Flash or OTP Memory
    • Zero wait state / low latency operation
    Block Diagram -- AHB Internal SRAM Controller
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